7 lines
190 B
VHDL
7 lines
190 B
VHDL
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ARCHITECTURE rtl OF bramAddrReducer IS
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BEGIN
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-- +2 to srr(2) the address (as it makes +4)
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addrOut <= std_ulogic_vector(addrIn(addrOut'high+2 downto addrOut'low+2));
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END ARCHITECTURE rtl;
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