19 lines
543 B
VHDL
19 lines
543 B
VHDL
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ARCHITECTURE rtl OF instrDecoder IS
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BEGIN
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decode : process(op)
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begin
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case op is
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when "0000011" => immSrc <= "00"; -- lw
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when "0100011" => immSrc <= "01"; -- sw
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when "0110011" => immSrc <= "--"; -- R-type
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when "1100011" => immSrc <= "10"; -- beq
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when "0010011" => immSrc <= "00"; -- l-type ALU
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when "1101111" => immSrc <= "11"; -- jal
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when others => immSrc <= "--"; -- unknwon
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end case;
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end process decode;
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END ARCHITECTURE rtl;
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