4838 lines
58 KiB
Plaintext
4838 lines
58 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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instances [
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(Instance
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name "I1"
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duLibraryName "Beamer"
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duName "beamerPeriphOperator"
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elements [
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(GiElement
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name "updatePeriodBitNb"
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type "positive"
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value "updatePeriodBitNb"
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)
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(GiElement
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name "signalBitNb"
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type "positive"
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value "signalBitNb"
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)
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]
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mwi 0
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uid 16094,0
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)
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(Instance
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name "I0"
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duLibraryName "Beamer"
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duName "beamerPeriphRegisters"
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elements [
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(GiElement
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name "pindex"
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type "natural"
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value "pindex"
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)
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(GiElement
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name "paddr"
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type "positive"
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value "paddr"
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)
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(GiElement
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name "pmask"
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type "positive"
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value "pmask"
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)
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(GiElement
|
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name "updatePeriodBitNb"
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type "positive"
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value "updatePeriodBitNb"
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)
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(GiElement
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name "signalBitNb"
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type "positive"
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value "signalBitNb"
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)
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(GiElement
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name "patternAddressBitNb"
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type "positive"
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value "patternAddressBitNb"
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)
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(GiElement
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name "testOutBitNb"
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type "positive"
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value "testOutBitNb"
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)
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]
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mwi 0
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uid 16456,0
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)
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]
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embeddedInstances [
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(EmbeddedInstance
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name "eb1"
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number "1"
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)
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(EmbeddedInstance
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name "eb2"
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number "2"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hdl"
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)
|
|
(vvPair
|
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variable "HDSDir"
|
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds"
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|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamer@periph\\struct.bd.info"
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)
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(vvPair
|
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamer@periph\\struct.bd.user"
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)
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(vvPair
|
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variable "SourceDir"
|
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds"
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)
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(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
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)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "struct"
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|
)
|
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(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
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)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
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)
|
|
(vvPair
|
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variable "config"
|
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value "%(unit)_%(view)_config"
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)
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(vvPair
|
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variable "d"
|
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamer@periph"
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)
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(vvPair
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variable "d_logical"
|
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamerPeriph"
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)
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(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
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)
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(vvPair
|
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variable "day"
|
|
value "ven."
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)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
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)
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|
(vvPair
|
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variable "designName"
|
|
value "$DESIGN_NAME"
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)
|
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(vvPair
|
|
variable "entity_name"
|
|
value "beamerPeriph"
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)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "struct.bd"
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|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
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)
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(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
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|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
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)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
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|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
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|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:01:30"
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|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
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|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
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|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip"
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|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
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)
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|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
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)
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|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
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|
value "$SCRATCH_DIR/SystemOnChip"
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)
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|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
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)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
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|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "beamerPeriph"
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)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
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|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
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|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamer@periph\\struct.bd"
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)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamerPeriph\\struct.bd"
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|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
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|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
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|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
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)
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(vvPair
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|
variable "task_DesignCompilerPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_HDSPath"
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value "$HDS_HOME"
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)
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(vvPair
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variable "task_ISEBinPath"
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value "$ISE_HOME"
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)
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(vvPair
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variable "task_ISEPath"
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value "$ISE_WORK_DIR"
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)
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(vvPair
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variable "task_LeonardoPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_ModelSimPath"
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value "$MODELSIM_HOME/modeltech/bin"
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)
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(vvPair
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variable "task_NC"
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value "<TBD>"
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)
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(vvPair
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variable "task_PrecisionRTLPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_QuestaSimPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_VCSPath"
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value "<TBD>"
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)
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(vvPair
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variable "this_ext"
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value "bd"
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)
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(vvPair
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variable "this_file"
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value "struct"
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)
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(vvPair
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variable "this_file_logical"
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value "struct"
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)
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(vvPair
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variable "time"
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value "15:01:30"
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)
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(vvPair
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variable "unit"
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value "beamerPeriph"
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(vvPair
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variable "user"
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value "axel.amand"
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(vvPair
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variable "version"
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value "2019.2 (Build 5)"
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(vvPair
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variable "view"
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value "struct"
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(vvPair
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variable "year"
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value "2023"
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)
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(vvPair
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variable "yy"
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value "23"
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]
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tg (WTG
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tm "WireNameMgr"
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n "outY"
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tg (WTG
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uid 6503,0
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decl (Decl
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va (VaSet
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va (VaSet
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uid 13130,0
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uid 13131,0
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tg (WTG
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uid 13140,0
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decl (Decl
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n "apbi"
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uid 13375,0
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ju 2
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blo "15000,3500"
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tm "WireNameMgr"
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uid 13385,0
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uid 14916,0
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uid 14921,0
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commentText (CommentText
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va (VaSet
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va (VaSet
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tm "HdlTextMgr"
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ttg (MlTextGroup
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uid 14918,0
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ps "CenterOffsetStrategy"
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tm "HdlTextNameMgr"
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uid 14920,0
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va (VaSet
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st "1"
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blo "18400,19000"
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tm "HdlTextNumberMgr"
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*30 (Net
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uid 14974,0
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decl (Decl
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declText (MLText
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uid 14975,0
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va (VaSet
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decl (Decl
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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uid 15207,0
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decl (Decl
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|
n "interpolateLin"
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|
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declText (MLText
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va (VaSet
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|
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|
*33 (Net
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|
uid 15213,0
|
|
decl (Decl
|
|
n "updatePeriod"
|
|
t "unsigned"
|
|
b "(updatePeriodBitNb-1 DOWNTO 0)"
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|
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|
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|
declText (MLText
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|
uid 15214,0
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va (VaSet
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|
font "Verdana,8,0"
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|
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|
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*34 (Net
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uid 15462,0
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decl (Decl
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n "memX"
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|
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declText (MLText
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uid 15463,0
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thePort (LogicalPort
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n "memX"
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*53 (CptPort
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uid 16090,0
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tg (CPTG
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uid 16093,0
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thePort (LogicalPort
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m 1
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n "newPolynom"
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|
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suid 2019,0
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)
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ttg (MlTextGroup
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tm "BdLibraryNameMgr"
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blo "66600,21000"
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tm "CptNameMgr"
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*56 (Text
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font "Verdana,9,1"
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st "I1"
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blo "66600,22200"
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tm "InstanceNameMgr"
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ga (GenericAssociation
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uid 16100,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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uid 16101,0
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text (MLText
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uid 16102,0
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va (VaSet
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font "Verdana,8,0"
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st "updatePeriodBitNb = updatePeriodBitNb ( positive )
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signalBitNb = signalBitNb ( positive ) "
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header ""
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elements [
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name "signalBitNb"
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|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*57 (Net
|
|
uid 16103,0
|
|
decl (Decl
|
|
n "newPolynom"
|
|
t "std_ulogic"
|
|
o 15
|
|
suid 83,0
|
|
)
|
|
declText (MLText
|
|
uid 16104,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,44600,18100,45600"
|
|
st "SIGNAL newPolynom : std_ulogic"
|
|
)
|
|
)
|
|
*58 (SaComponent
|
|
uid 16456,0
|
|
optionalChildren [
|
|
*59 (CptPort
|
|
uid 16412,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16413,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "33250,10625,34000,11375"
|
|
)
|
|
tg (CPTG
|
|
uid 16414,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16415,0
|
|
va (VaSet
|
|
)
|
|
xt "35000,10400,38400,11600"
|
|
st "clock"
|
|
blo "35000,11400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*60 (CptPort
|
|
uid 16416,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16417,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "33250,625,34000,1375"
|
|
)
|
|
tg (CPTG
|
|
uid 16418,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16419,0
|
|
va (VaSet
|
|
)
|
|
xt "35000,400,37800,1600"
|
|
st "apbi"
|
|
blo "35000,1400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "apbi"
|
|
t "apb_slv_in_type"
|
|
o 1
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*61 (CptPort
|
|
uid 16420,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16421,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "33250,2625,34000,3375"
|
|
)
|
|
tg (CPTG
|
|
uid 16422,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16423,0
|
|
va (VaSet
|
|
)
|
|
xt "35000,2400,38100,3600"
|
|
st "apbo"
|
|
blo "35000,3400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "apbo"
|
|
t "apb_slv_out_type"
|
|
o 3
|
|
suid 11,0
|
|
)
|
|
)
|
|
)
|
|
*62 (CptPort
|
|
uid 16424,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16425,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41625,-3750,42375,-3000"
|
|
)
|
|
tg (CPTG
|
|
uid 16426,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16427,0
|
|
va (VaSet
|
|
)
|
|
xt "40000,-2000,44600,-800"
|
|
st "testOut"
|
|
blo "40000,-1000"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "testOut"
|
|
t "std_ulogic_vector"
|
|
b "(1 TO testOutBitNb)"
|
|
o 4
|
|
suid 12,0
|
|
)
|
|
)
|
|
)
|
|
*63 (CptPort
|
|
uid 16428,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16429,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50000,625,50750,1375"
|
|
)
|
|
tg (CPTG
|
|
uid 16430,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16431,0
|
|
va (VaSet
|
|
)
|
|
xt "46700,400,49000,1600"
|
|
st "run"
|
|
ju 2
|
|
blo "49000,1400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "run"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 2014,0
|
|
)
|
|
)
|
|
)
|
|
*64 (CptPort
|
|
uid 16432,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16433,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50000,4625,50750,5375"
|
|
)
|
|
tg (CPTG
|
|
uid 16434,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16435,0
|
|
va (VaSet
|
|
)
|
|
xt "41000,4400,49000,5600"
|
|
st "updatePeriod"
|
|
ju 2
|
|
blo "49000,5400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "updatePeriod"
|
|
t "unsigned"
|
|
b "(updatePeriodBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 2015,0
|
|
)
|
|
)
|
|
)
|
|
*65 (CptPort
|
|
uid 16436,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16437,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50000,8625,50750,9375"
|
|
)
|
|
tg (CPTG
|
|
uid 16438,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16439,0
|
|
va (VaSet
|
|
)
|
|
xt "45200,8400,49000,9600"
|
|
st "memX"
|
|
ju 2
|
|
blo "49000,9400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "memX"
|
|
t "std_ulogic_vector"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 2016,0
|
|
)
|
|
)
|
|
)
|
|
*66 (CptPort
|
|
uid 16440,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16441,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50000,10625,50750,11375"
|
|
)
|
|
tg (CPTG
|
|
uid 16442,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16443,0
|
|
va (VaSet
|
|
)
|
|
xt "45200,10400,49000,11600"
|
|
st "memY"
|
|
ju 2
|
|
blo "49000,11400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "memY"
|
|
t "std_ulogic_vector"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 2017,0
|
|
)
|
|
)
|
|
)
|
|
*67 (CptPort
|
|
uid 16444,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16445,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50000,2625,50750,3375"
|
|
)
|
|
tg (CPTG
|
|
uid 16446,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16447,0
|
|
va (VaSet
|
|
)
|
|
xt "40700,2400,49000,3600"
|
|
st "interpolateLin"
|
|
ju 2
|
|
blo "49000,3400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "interpolateLin"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 2018,0
|
|
)
|
|
)
|
|
)
|
|
*68 (CptPort
|
|
uid 16448,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16449,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "33250,12625,34000,13375"
|
|
)
|
|
tg (CPTG
|
|
uid 16450,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16451,0
|
|
va (VaSet
|
|
)
|
|
xt "35000,12400,38300,13600"
|
|
st "reset"
|
|
blo "35000,13400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 2021,0
|
|
)
|
|
)
|
|
)
|
|
*69 (CptPort
|
|
uid 16452,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 16453,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50000,6625,50750,7375"
|
|
)
|
|
tg (CPTG
|
|
uid 16454,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 16455,0
|
|
va (VaSet
|
|
)
|
|
xt "41400,6400,49000,7600"
|
|
st "newPolynom"
|
|
ju 2
|
|
blo "49000,7400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "newPolynom"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 2022,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 16457,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "34000,-3000,50000,15000"
|
|
)
|
|
oxt "36000,12000,52000,30000"
|
|
ttg (MlTextGroup
|
|
uid 16458,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*70 (Text
|
|
uid 16459,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "34600,14800,39000,16000"
|
|
st "Beamer"
|
|
blo "34600,15800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*71 (Text
|
|
uid 16460,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "34600,16000,48000,17200"
|
|
st "beamerPeriphRegisters"
|
|
blo "34600,17000"
|
|
tm "CptNameMgr"
|
|
)
|
|
*72 (Text
|
|
uid 16461,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "34600,17200,36300,18400"
|
|
st "I0"
|
|
blo "34600,18200"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 16462,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 16463,0
|
|
text (MLText
|
|
uid 16464,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "34000,18600,59800,25600"
|
|
st "pindex = pindex ( natural )
|
|
paddr = paddr ( positive )
|
|
pmask = pmask ( positive )
|
|
updatePeriodBitNb = updatePeriodBitNb ( positive )
|
|
signalBitNb = signalBitNb ( positive )
|
|
patternAddressBitNb = patternAddressBitNb ( positive )
|
|
testOutBitNb = testOutBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "pindex"
|
|
type "natural"
|
|
value "pindex"
|
|
)
|
|
(GiElement
|
|
name "paddr"
|
|
type "positive"
|
|
value "paddr"
|
|
)
|
|
(GiElement
|
|
name "pmask"
|
|
type "positive"
|
|
value "pmask"
|
|
)
|
|
(GiElement
|
|
name "updatePeriodBitNb"
|
|
type "positive"
|
|
value "updatePeriodBitNb"
|
|
)
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
(GiElement
|
|
name "patternAddressBitNb"
|
|
type "positive"
|
|
value "patternAddressBitNb"
|
|
)
|
|
(GiElement
|
|
name "testOutBitNb"
|
|
type "positive"
|
|
value "testOutBitNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*73 (Wire
|
|
uid 115,0
|
|
shape (OrthoPolyLine
|
|
uid 116,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "82750,1000,90000,1000"
|
|
pts [
|
|
"82750,1000"
|
|
"90000,1000"
|
|
]
|
|
)
|
|
start &45
|
|
end &12
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 119,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 120,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "87000,-400,90700,1000"
|
|
st "outX"
|
|
blo "87000,800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &13
|
|
)
|
|
*74 (Wire
|
|
uid 129,0
|
|
shape (OrthoPolyLine
|
|
uid 130,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "82750,3000,90000,3000"
|
|
pts [
|
|
"82750,3000"
|
|
"90000,3000"
|
|
]
|
|
)
|
|
start &47
|
|
end &14
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 133,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 134,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "87000,1600,90600,3000"
|
|
st "outY"
|
|
blo "87000,2800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &15
|
|
)
|
|
*75 (Wire
|
|
uid 5086,0
|
|
shape (OrthoPolyLine
|
|
uid 5087,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "82750,7000,90000,7000"
|
|
pts [
|
|
"90000,7000"
|
|
"82750,7000"
|
|
]
|
|
)
|
|
start &16
|
|
end &48
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 5090,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 5091,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "85000,5600,91900,7000"
|
|
st "selSinCos"
|
|
blo "85000,6800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*76 (Wire
|
|
uid 13134,0
|
|
shape (OrthoPolyLine
|
|
uid 13135,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "18000,1000,33250,1000"
|
|
pts [
|
|
"18000,1000"
|
|
"33250,1000"
|
|
]
|
|
)
|
|
start &18
|
|
end &60
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 13138,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 13139,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "18000,-400,21500,1000"
|
|
st "apbi"
|
|
blo "18000,800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*77 (Wire
|
|
uid 13379,0
|
|
shape (OrthoPolyLine
|
|
uid 13380,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "18000,3000,33250,3000"
|
|
pts [
|
|
"33250,3000"
|
|
"18000,3000"
|
|
]
|
|
)
|
|
start &61
|
|
end &20
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 13383,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 13384,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "18000,1600,22000,3000"
|
|
st "apbo"
|
|
blo "18000,2800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &21
|
|
)
|
|
*78 (Wire
|
|
uid 13628,0
|
|
shape (OrthoPolyLine
|
|
uid 13629,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "10000,15000,18000,15000"
|
|
pts [
|
|
"10000,15000"
|
|
"18000,15000"
|
|
]
|
|
)
|
|
start &22
|
|
end &26
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 13632,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 13633,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "10000,13600,15700,15000"
|
|
st "reset_n"
|
|
blo "10000,14800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &23
|
|
)
|
|
*79 (Wire
|
|
uid 14878,0
|
|
shape (OrthoPolyLine
|
|
uid 14879,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "18000,11000,33250,11000"
|
|
pts [
|
|
"33250,11000"
|
|
"18000,11000"
|
|
]
|
|
)
|
|
start &59
|
|
end &25
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 14882,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 14883,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "18000,9600,21800,11000"
|
|
st "clock"
|
|
blo "18000,10800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &24
|
|
)
|
|
*80 (Wire
|
|
uid 14976,0
|
|
shape (OrthoPolyLine
|
|
uid 14977,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "26000,13000,33250,15000"
|
|
pts [
|
|
"33250,13000"
|
|
"30000,13000"
|
|
"30000,15000"
|
|
"26000,15000"
|
|
]
|
|
)
|
|
start &68
|
|
end &26
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 14980,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 14981,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "29000,11600,33100,13000"
|
|
st "reset"
|
|
blo "29000,12800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &30
|
|
)
|
|
*81 (Wire
|
|
uid 15203,0
|
|
shape (OrthoPolyLine
|
|
uid 15204,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "50750,1000,65250,1000"
|
|
pts [
|
|
"50750,1000"
|
|
"65250,1000"
|
|
]
|
|
)
|
|
start &63
|
|
end &44
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 15205,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 15206,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "52750,-400,55650,1000"
|
|
st "run"
|
|
blo "52750,800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &31
|
|
)
|
|
*82 (Wire
|
|
uid 15209,0
|
|
shape (OrthoPolyLine
|
|
uid 15210,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "50750,3000,65250,3000"
|
|
pts [
|
|
"50750,3000"
|
|
"65250,3000"
|
|
]
|
|
)
|
|
start &67
|
|
end &49
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 15211,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 15212,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "52750,1600,63050,3000"
|
|
st "interpolateLin"
|
|
blo "52750,2800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &32
|
|
)
|
|
*83 (Wire
|
|
uid 15215,0
|
|
shape (OrthoPolyLine
|
|
uid 15216,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "50750,5000,65250,5000"
|
|
pts [
|
|
"50750,5000"
|
|
"65250,5000"
|
|
]
|
|
)
|
|
start &64
|
|
end &50
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 15217,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 15218,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "52750,3600,62850,5000"
|
|
st "updatePeriod"
|
|
blo "52750,4800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &33
|
|
)
|
|
*84 (Wire
|
|
uid 15464,0
|
|
shape (OrthoPolyLine
|
|
uid 15465,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "50750,9000,65250,9000"
|
|
pts [
|
|
"50750,9000"
|
|
"65250,9000"
|
|
]
|
|
)
|
|
start &65
|
|
end &51
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 15466,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 15467,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "52750,7600,57350,9000"
|
|
st "memX"
|
|
blo "52750,8800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &34
|
|
)
|
|
*85 (Wire
|
|
uid 15470,0
|
|
shape (OrthoPolyLine
|
|
uid 15471,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "50750,11000,65250,11000"
|
|
pts [
|
|
"50750,11000"
|
|
"65250,11000"
|
|
]
|
|
)
|
|
start &66
|
|
end &52
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 15472,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 15473,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "52750,9600,57250,11000"
|
|
st "memY"
|
|
blo "52750,10800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &35
|
|
)
|
|
*86 (Wire
|
|
uid 15527,0
|
|
shape (OrthoPolyLine
|
|
uid 15528,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "62000,15000,65250,15000"
|
|
pts [
|
|
"65250,15000"
|
|
"62000,15000"
|
|
]
|
|
)
|
|
start &43
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 15533,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 15534,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "61000,13600,64800,15000"
|
|
st "clock"
|
|
blo "61000,14800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &24
|
|
)
|
|
*87 (Wire
|
|
uid 15535,0
|
|
shape (OrthoPolyLine
|
|
uid 15536,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "62000,17000,65250,17000"
|
|
pts [
|
|
"65250,17000"
|
|
"62000,17000"
|
|
]
|
|
)
|
|
start &46
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 15541,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 15542,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "61000,15600,65100,17000"
|
|
st "reset"
|
|
blo "61000,16800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &30
|
|
)
|
|
*88 (Wire
|
|
uid 15576,0
|
|
shape (OrthoPolyLine
|
|
uid 15577,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "42000,-7000,50000,-3750"
|
|
pts [
|
|
"42000,-3750"
|
|
"42000,-7000"
|
|
"50000,-7000"
|
|
]
|
|
)
|
|
start &62
|
|
end &37
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 15580,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 15581,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "45000,-8400,50600,-7000"
|
|
st "testOut"
|
|
blo "45000,-7200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &36
|
|
)
|
|
*89 (Wire
|
|
uid 16105,0
|
|
shape (OrthoPolyLine
|
|
uid 16106,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "50750,7000,65250,7000"
|
|
pts [
|
|
"50750,7000"
|
|
"65250,7000"
|
|
]
|
|
)
|
|
start &69
|
|
end &53
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 16107,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 16108,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "52750,5600,62350,7000"
|
|
st "newPolynom"
|
|
blo "52750,6800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &57
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 0
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *90 (PackageList
|
|
uid 42,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*91 (Text
|
|
uid 43,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,-25000,6900,-24000"
|
|
st "Package List"
|
|
blo "0,-24200"
|
|
)
|
|
*92 (MLText
|
|
uid 44,0
|
|
va (VaSet
|
|
)
|
|
xt "0,-24000,17500,-20400"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.ALL;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 45,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*93 (Text
|
|
uid 46,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,0,30200,1000"
|
|
st "Compiler Directives"
|
|
blo "20000,800"
|
|
)
|
|
*94 (Text
|
|
uid 47,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,1000,32200,2000"
|
|
st "Pre-module directives:"
|
|
blo "20000,1800"
|
|
)
|
|
*95 (MLText
|
|
uid 48,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,2000,32100,4400"
|
|
st "`resetall
|
|
`timescale 1ns/10ps"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*96 (Text
|
|
uid 49,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,4000,32800,5000"
|
|
st "Post-module directives:"
|
|
blo "20000,4800"
|
|
)
|
|
*97 (MLText
|
|
uid 50,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,0,20000,0"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*98 (Text
|
|
uid 51,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,5000,32400,6000"
|
|
st "End-module directives:"
|
|
blo "20000,5800"
|
|
)
|
|
*99 (MLText
|
|
uid 52,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,6000,20000,6000"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
]
|
|
associable 1
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"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
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|
stg "STSignalDisplayStrategy"
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f (Text
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|
va (VaSet
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|
font "Verdana,12,0"
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)
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|
xt "0,0,3900,1400"
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|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
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|
shape (OrthoPolyLine
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|
va (VaSet
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|
vasetType 3
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|
lineStyle 3
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|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
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|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
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|
shape (RectFrame
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|
va (VaSet
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|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
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|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*117 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*118 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*119 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*120 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,27000,7000,28000"
|
|
st "Declarations"
|
|
blo "0,27800"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,28000,3400,29000"
|
|
st "Ports:"
|
|
blo "0,28800"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,35400,4800,36400"
|
|
st "Pre User:"
|
|
blo "0,36200"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,36400,23000,39400"
|
|
st "constant signalBitNb: positive := 16;
|
|
constant updatePeriodBitNb : positive := 16;
|
|
constant patternAddressBitNb : positive := 10;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,38800,9000,39800"
|
|
st "Diagram Signals:"
|
|
blo "0,39600"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,27000,6000,28000"
|
|
st "Post User:"
|
|
blo "0,27800"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,27000,0,27000"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
ordering 1
|
|
suid 83,0
|
|
usingSuid 1
|
|
emptyRow *121 (LEmptyRow
|
|
)
|
|
uid 10774,0
|
|
optionalChildren [
|
|
*122 (RefLabelRowHdr
|
|
)
|
|
*123 (TitleRowHdr
|
|
)
|
|
*124 (FilterRowHdr
|
|
)
|
|
*125 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*126 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*127 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*128 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*129 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*130 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*131 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*132 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*133 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*134 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outX"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 4,0
|
|
)
|
|
)
|
|
uid 10639,0
|
|
)
|
|
*135 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outY"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 5,0
|
|
)
|
|
)
|
|
uid 10641,0
|
|
)
|
|
*136 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 62,0
|
|
)
|
|
)
|
|
uid 10755,0
|
|
)
|
|
*137 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "apbi"
|
|
t "apb_slv_in_type"
|
|
o 2
|
|
suid 71,0
|
|
)
|
|
)
|
|
uid 13127,0
|
|
)
|
|
*138 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "apbo"
|
|
t "apb_slv_out_type"
|
|
o 5
|
|
suid 72,0
|
|
)
|
|
)
|
|
uid 13372,0
|
|
)
|
|
*139 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset_n"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 73,0
|
|
)
|
|
)
|
|
uid 13621,0
|
|
)
|
|
*140 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 74,0
|
|
)
|
|
)
|
|
uid 14914,0
|
|
)
|
|
*141 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 75,0
|
|
)
|
|
)
|
|
uid 14982,0
|
|
)
|
|
*142 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "run"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 76,0
|
|
)
|
|
)
|
|
uid 15219,0
|
|
)
|
|
*143 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "interpolateLin"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 77,0
|
|
)
|
|
)
|
|
uid 15221,0
|
|
)
|
|
*144 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "updatePeriod"
|
|
t "unsigned"
|
|
b "(updatePeriodBitNb-1 DOWNTO 0)"
|
|
o 12
|
|
suid 78,0
|
|
)
|
|
)
|
|
uid 15223,0
|
|
)
|
|
*145 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "memX"
|
|
t "std_ulogic_vector"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 13
|
|
suid 79,0
|
|
)
|
|
)
|
|
uid 15474,0
|
|
)
|
|
*146 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "memY"
|
|
t "std_ulogic_vector"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 14
|
|
suid 80,0
|
|
)
|
|
)
|
|
uid 15476,0
|
|
)
|
|
*147 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "testOut"
|
|
t "std_ulogic_vector"
|
|
b "(1 TO testOutBitNb)"
|
|
o 8
|
|
suid 81,0
|
|
)
|
|
)
|
|
uid 15588,0
|
|
)
|
|
*148 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "newPolynom"
|
|
t "std_ulogic"
|
|
o 15
|
|
suid 83,0
|
|
)
|
|
)
|
|
uid 16109,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 10787,0
|
|
optionalChildren [
|
|
*149 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *150 (MRCItem
|
|
litem &121
|
|
pos 15
|
|
dimension 20
|
|
)
|
|
uid 10789,0
|
|
optionalChildren [
|
|
*151 (MRCItem
|
|
litem &122
|
|
pos 0
|
|
dimension 20
|
|
uid 10790,0
|
|
)
|
|
*152 (MRCItem
|
|
litem &123
|
|
pos 1
|
|
dimension 23
|
|
uid 10791,0
|
|
)
|
|
*153 (MRCItem
|
|
litem &124
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 10792,0
|
|
)
|
|
*154 (MRCItem
|
|
litem &134
|
|
pos 1
|
|
dimension 20
|
|
uid 10640,0
|
|
)
|
|
*155 (MRCItem
|
|
litem &135
|
|
pos 2
|
|
dimension 20
|
|
uid 10642,0
|
|
)
|
|
*156 (MRCItem
|
|
litem &136
|
|
pos 5
|
|
dimension 20
|
|
uid 10756,0
|
|
)
|
|
*157 (MRCItem
|
|
litem &137
|
|
pos 0
|
|
dimension 20
|
|
uid 13126,0
|
|
)
|
|
*158 (MRCItem
|
|
litem &138
|
|
pos 4
|
|
dimension 20
|
|
uid 13371,0
|
|
)
|
|
*159 (MRCItem
|
|
litem &139
|
|
pos 3
|
|
dimension 20
|
|
uid 13620,0
|
|
)
|
|
*160 (MRCItem
|
|
litem &140
|
|
pos 6
|
|
dimension 20
|
|
uid 14915,0
|
|
)
|
|
*161 (MRCItem
|
|
litem &141
|
|
pos 8
|
|
dimension 20
|
|
uid 14983,0
|
|
)
|
|
*162 (MRCItem
|
|
litem &142
|
|
pos 9
|
|
dimension 20
|
|
uid 15220,0
|
|
)
|
|
*163 (MRCItem
|
|
litem &143
|
|
pos 10
|
|
dimension 20
|
|
uid 15222,0
|
|
)
|
|
*164 (MRCItem
|
|
litem &144
|
|
pos 11
|
|
dimension 20
|
|
uid 15224,0
|
|
)
|
|
*165 (MRCItem
|
|
litem &145
|
|
pos 12
|
|
dimension 20
|
|
uid 15475,0
|
|
)
|
|
*166 (MRCItem
|
|
litem &146
|
|
pos 13
|
|
dimension 20
|
|
uid 15477,0
|
|
)
|
|
*167 (MRCItem
|
|
litem &147
|
|
pos 7
|
|
dimension 20
|
|
uid 15589,0
|
|
)
|
|
*168 (MRCItem
|
|
litem &148
|
|
pos 14
|
|
dimension 20
|
|
uid 16110,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 10793,0
|
|
optionalChildren [
|
|
*169 (MRCItem
|
|
litem &125
|
|
pos 0
|
|
dimension 20
|
|
uid 10794,0
|
|
)
|
|
*170 (MRCItem
|
|
litem &127
|
|
pos 1
|
|
dimension 50
|
|
uid 10795,0
|
|
)
|
|
*171 (MRCItem
|
|
litem &128
|
|
pos 2
|
|
dimension 100
|
|
uid 10796,0
|
|
)
|
|
*172 (MRCItem
|
|
litem &129
|
|
pos 3
|
|
dimension 50
|
|
uid 10797,0
|
|
)
|
|
*173 (MRCItem
|
|
litem &130
|
|
pos 4
|
|
dimension 100
|
|
uid 10798,0
|
|
)
|
|
*174 (MRCItem
|
|
litem &131
|
|
pos 5
|
|
dimension 100
|
|
uid 10799,0
|
|
)
|
|
*175 (MRCItem
|
|
litem &132
|
|
pos 6
|
|
dimension 50
|
|
uid 10800,0
|
|
)
|
|
*176 (MRCItem
|
|
litem &133
|
|
pos 7
|
|
dimension 80
|
|
uid 10801,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 10788,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 10773,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *177 (LEmptyRow
|
|
)
|
|
uid 10803,0
|
|
optionalChildren [
|
|
*178 (RefLabelRowHdr
|
|
)
|
|
*179 (TitleRowHdr
|
|
)
|
|
*180 (FilterRowHdr
|
|
)
|
|
*181 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*182 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*183 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*184 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*185 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*186 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*187 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*188 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*189 (LogGeneric
|
|
generic (GiElement
|
|
name "testOutBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 12900,0
|
|
)
|
|
*190 (LogGeneric
|
|
generic (GiElement
|
|
name "pindex"
|
|
type "natural"
|
|
value "7"
|
|
)
|
|
uid 13874,0
|
|
)
|
|
*191 (LogGeneric
|
|
generic (GiElement
|
|
name "paddr"
|
|
type "positive"
|
|
value "16#003#"
|
|
)
|
|
uid 14113,0
|
|
)
|
|
*192 (LogGeneric
|
|
generic (GiElement
|
|
name "pmask"
|
|
type "positive"
|
|
value "16#FFF#"
|
|
)
|
|
uid 14352,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 10815,0
|
|
optionalChildren [
|
|
*193 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *194 (MRCItem
|
|
litem &177
|
|
pos 4
|
|
dimension 20
|
|
)
|
|
uid 10817,0
|
|
optionalChildren [
|
|
*195 (MRCItem
|
|
litem &178
|
|
pos 0
|
|
dimension 20
|
|
uid 10818,0
|
|
)
|
|
*196 (MRCItem
|
|
litem &179
|
|
pos 1
|
|
dimension 23
|
|
uid 10819,0
|
|
)
|
|
*197 (MRCItem
|
|
litem &180
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 10820,0
|
|
)
|
|
*198 (MRCItem
|
|
litem &189
|
|
pos 3
|
|
dimension 20
|
|
uid 12899,0
|
|
)
|
|
*199 (MRCItem
|
|
litem &190
|
|
pos 0
|
|
dimension 20
|
|
uid 13873,0
|
|
)
|
|
*200 (MRCItem
|
|
litem &191
|
|
pos 1
|
|
dimension 20
|
|
uid 14112,0
|
|
)
|
|
*201 (MRCItem
|
|
litem &192
|
|
pos 2
|
|
dimension 20
|
|
uid 14351,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 10821,0
|
|
optionalChildren [
|
|
*202 (MRCItem
|
|
litem &181
|
|
pos 0
|
|
dimension 20
|
|
uid 10822,0
|
|
)
|
|
*203 (MRCItem
|
|
litem &183
|
|
pos 1
|
|
dimension 50
|
|
uid 10823,0
|
|
)
|
|
*204 (MRCItem
|
|
litem &184
|
|
pos 2
|
|
dimension 100
|
|
uid 10824,0
|
|
)
|
|
*205 (MRCItem
|
|
litem &185
|
|
pos 3
|
|
dimension 100
|
|
uid 10825,0
|
|
)
|
|
*206 (MRCItem
|
|
litem &186
|
|
pos 4
|
|
dimension 50
|
|
uid 10826,0
|
|
)
|
|
*207 (MRCItem
|
|
litem &187
|
|
pos 5
|
|
dimension 50
|
|
uid 10827,0
|
|
)
|
|
*208 (MRCItem
|
|
litem &188
|
|
pos 6
|
|
dimension 80
|
|
uid 10828,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 10816,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 10802,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|