4499 lines
55 KiB
Plaintext
4499 lines
55 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "AhbLite"
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unitName "ahbLite"
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)
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]
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instances [
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(Instance
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name "I_tester"
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duLibraryName "SystemOnChip_test"
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duName "ahbBeamer_tester"
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elements [
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(GiElement
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name "patternAddressBitNb"
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type "positive"
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|
value "patternAddressBitNb"
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)
|
|
(GiElement
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|
name "signalBitNb"
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|
type "positive"
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|
value "signalBitNb"
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|
)
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|
(GiElement
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name "clockFrequency"
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|
type "real"
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value "clockFrequency"
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)
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]
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mwi 0
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|
uid 12657,0
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)
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|
(Instance
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|
name "I_filt"
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duLibraryName "WaveformGenerator"
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|
duName "lowpass"
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|
elements [
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|
(GiElement
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name "signalBitNb"
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|
type "positive"
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value "signalBitNb"
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)
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|
(GiElement
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name "shiftBitNb"
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|
type "positive"
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value "lowpassShiftBitNb"
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|
)
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]
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|
mwi 0
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|
uid 13849,0
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)
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(Instance
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name "I_DUT"
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duLibraryName "SystemOnChip"
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duName "ahbBeamer"
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elements [
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|
(GiElement
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name "patternAddressBitNb"
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|
type "positive"
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|
value "patternAddressBitNb"
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)
|
|
(GiElement
|
|
name "testOutBitNb"
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|
type "positive"
|
|
value "testOutBitNb"
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|
)
|
|
]
|
|
mwi 0
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|
uid 14527,0
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)
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]
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embeddedInstances [
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|
(EmbeddedInstance
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name "eb2"
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number "2"
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)
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]
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libraryRefs [
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"ieee"
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|
"AhbLite"
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|
]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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|
variable "HDLDir"
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|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hdl"
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)
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|
(vvPair
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|
variable "HDSDir"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
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)
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|
(vvPair
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|
variable "SideDataDesignDir"
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|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahb@beamer_tb\\struct.bd.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahb@beamer_tb\\struct.bd.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
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|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "struct"
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|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
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|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahb@beamer_tb"
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)
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|
(vvPair
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|
variable "d_logical"
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|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahbBeamer_tb"
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)
|
|
(vvPair
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|
variable "date"
|
|
value "28.04.2023"
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|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
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|
variable "dd"
|
|
value "28"
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)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
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|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "ahbBeamer_tb"
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)
|
|
(vvPair
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|
variable "ext"
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|
value "<TBD>"
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)
|
|
(vvPair
|
|
variable "f"
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|
value "struct.bd"
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|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "struct.bd"
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)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
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|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
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)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
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)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:04:15"
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|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
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|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
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)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
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|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip_test"
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)
|
|
(vvPair
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|
variable "library_downstream_ModelSim"
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
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|
value "$SCRATCH_DIR/SystemOnChip_test"
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)
|
|
(vvPair
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|
variable "mm"
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|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "ahbBeamer_tb"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahb@beamer_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahbBeamer_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "15:04:15"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "ahbBeamer_tb"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
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)
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LanguageMgr "Vhdl2008LangMgr"
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uid 198,0
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n "hSel"
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va (VaSet
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decl (Decl
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n "hWrite"
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)
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declText (MLText
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va (VaSet
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uid 12611,0
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decl (Decl
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n "hTrans"
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declText (MLText
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va (VaSet
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isHidden 1
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uid 12619,0
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decl (Decl
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n "hWData"
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b "(ahbDataBitNb-1 DOWNTO 0)"
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)
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declText (MLText
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uid 12620,0
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va (VaSet
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isHidden 1
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)
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st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
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)
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uid 12627,0
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decl (Decl
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n "hAddr"
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t "unsigned"
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b "( ahbAddressBitNb-1 DOWNTO 0 )"
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suid 117,0
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)
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declText (MLText
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uid 12628,0
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va (VaSet
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isHidden 1
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)
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st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 )"
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)
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)
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uid 12657,0
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shape (Rectangle
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uid 12658,0
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va (VaSet
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vasetType 1
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fg "39936,56832,65280"
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)
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)
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ttg (MlTextGroup
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uid 12659,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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va (VaSet
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blo "39400,78100"
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tm "BdLibraryNameMgr"
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)
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va (VaSet
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font "Verdana,12,0"
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)
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st "ahbBeamer_tester"
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blo "39400,79500"
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tm "BlkNameMgr"
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)
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uid 12662,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "39400,79700,45300,81100"
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st "I_tester"
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blo "39400,80900"
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tm "InstanceNameMgr"
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)
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]
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)
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ga (GenericAssociation
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uid 12663,0
|
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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uid 12664,0
|
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text (MLText
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uid 12665,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "39400,82300,65200,85300"
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st "patternAddressBitNb = patternAddressBitNb ( positive )
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signalBitNb = signalBitNb ( positive )
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)
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header ""
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)
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elements [
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name "patternAddressBitNb"
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value "patternAddressBitNb"
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)
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(GiElement
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name "signalBitNb"
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type "positive"
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value "signalBitNb"
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)
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(GiElement
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name "clockFrequency"
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type "real"
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value "clockFrequency"
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)
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viewicon (ZoomableIcon
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uid 12742,0
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sl 0
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va (VaSet
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vasetType 1
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fg "49152,49152,49152"
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)
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xt "39250,75250,40750,76750"
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iconMaskName "VhdlFileViewIcon.msk"
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ftype 10
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)
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viewiconposition 0
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uid 13629,0
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decl (Decl
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n "selSinCos"
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t "std_ulogic"
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suid 120,0
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declText (MLText
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uid 13630,0
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va (VaSet
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isHidden 1
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)
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st "SIGNAL selSinCos : std_ulogic"
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)
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)
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*27 (Net
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uid 13637,0
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decl (Decl
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n "outY"
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t "std_ulogic"
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o 15
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|
suid 121,0
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)
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declText (MLText
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uid 13638,0
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va (VaSet
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isHidden 1
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)
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st "SIGNAL outY : std_ulogic"
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)
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)
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*28 (Net
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uid 13645,0
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decl (Decl
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n "outX"
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t "std_ulogic"
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o 14
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|
suid 122,0
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)
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declText (MLText
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uid 13646,0
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va (VaSet
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isHidden 1
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st "SIGNAL outX : std_ulogic"
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uid 13840,0
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optionalChildren [
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*30 (EmbeddedText
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uid 13845,0
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commentText (CommentText
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|
uid 13846,0
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ps "CenterOffsetStrategy"
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shape (Rectangle
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uid 13847,0
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va (VaSet
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|
vasetType 1
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|
fg "65535,65535,65535"
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|
lineStyle 2
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)
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|
xt "85000,28000,101000,30000"
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)
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|
oxt "0,0,18000,5000"
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|
text (MLText
|
|
uid 13848,0
|
|
va (VaSet
|
|
)
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|
xt "85200,28200,100700,29400"
|
|
st "
|
|
lowpassInY <= (others => outY);
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|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
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|
visibleHeight 2000
|
|
visibleWidth 16000
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)
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|
)
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)
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|
]
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shape (Rectangle
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|
uid 13841,0
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va (VaSet
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vasetType 1
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|
fg "65535,65535,32768"
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)
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)
|
|
oxt "0,0,8000,10000"
|
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ttg (MlTextGroup
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|
uid 13842,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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uid 13843,0
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va (VaSet
|
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)
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xt "85400,31000,88000,32200"
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|
st "eb2"
|
|
blo "85400,32000"
|
|
tm "HdlTextNameMgr"
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)
|
|
*32 (Text
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|
uid 13844,0
|
|
va (VaSet
|
|
)
|
|
xt "85400,32000,86800,33200"
|
|
st "2"
|
|
blo "85400,33000"
|
|
tm "HdlTextNumberMgr"
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)
|
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]
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)
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)
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|
*33 (SaComponent
|
|
uid 13849,0
|
|
optionalChildren [
|
|
*34 (CptPort
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|
uid 13858,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 13859,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "100250,44625,101000,45375"
|
|
)
|
|
tg (CPTG
|
|
uid 13860,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 13861,0
|
|
va (VaSet
|
|
)
|
|
xt "102000,44400,105400,45600"
|
|
st "clock"
|
|
blo "102000,45400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
)
|
|
)
|
|
)
|
|
*35 (CptPort
|
|
uid 13862,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 13863,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "117000,40625,117750,41375"
|
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)
|
|
tg (CPTG
|
|
uid 13864,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 13865,0
|
|
va (VaSet
|
|
)
|
|
xt "108700,40400,116000,41600"
|
|
st "lowpassOut"
|
|
ju 2
|
|
blo "116000,41400"
|
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)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "lowpassOut"
|
|
t "unsigned"
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|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
)
|
|
)
|
|
)
|
|
*36 (CptPort
|
|
uid 13866,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 13867,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "100250,46625,101000,47375"
|
|
)
|
|
tg (CPTG
|
|
uid 13868,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 13869,0
|
|
va (VaSet
|
|
)
|
|
xt "102000,46400,105300,47600"
|
|
st "reset"
|
|
blo "102000,47400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
)
|
|
)
|
|
)
|
|
*37 (CptPort
|
|
uid 13870,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 13871,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "100250,40625,101000,41375"
|
|
)
|
|
tg (CPTG
|
|
uid 13872,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 13873,0
|
|
va (VaSet
|
|
)
|
|
xt "102000,40400,107800,41600"
|
|
st "lowpassIn"
|
|
blo "102000,41400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "lowpassIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
)
|
|
)
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)
|
|
]
|
|
shape (Rectangle
|
|
uid 13850,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
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|
bg "0,65535,0"
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|
lineColor "0,32896,0"
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|
lineWidth 2
|
|
)
|
|
xt "101000,37000,117000,49000"
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)
|
|
oxt "32000,10000,48000,22000"
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ttg (MlTextGroup
|
|
uid 13851,0
|
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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|
*38 (Text
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uid 13852,0
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va (VaSet
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font "Verdana,9,1"
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)
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|
xt "101600,48800,113100,50000"
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|
st "WaveformGenerator"
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|
blo "101600,49800"
|
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tm "BdLibraryNameMgr"
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)
|
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*39 (Text
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uid 13853,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "101600,50000,106200,51200"
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st "lowpass"
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blo "101600,51000"
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tm "CptNameMgr"
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)
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*40 (Text
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uid 13854,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "101600,51200,104900,52400"
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st "I_filt"
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blo "101600,52200"
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tm "InstanceNameMgr"
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)
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]
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)
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ga (GenericAssociation
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uid 13855,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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uid 13856,0
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text (MLText
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uid 13857,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "101000,52600,121800,54600"
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st "signalBitNb = signalBitNb ( positive )
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)
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header ""
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)
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elements [
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name "signalBitNb"
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type "positive"
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value "signalBitNb"
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)
|
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(GiElement
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|
name "shiftBitNb"
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type "positive"
|
|
value "lowpassShiftBitNb"
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)
|
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)
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ordering 1
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portVis (PortSigDisplay
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sTC 0
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)
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archFileType "UNKNOWN"
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)
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uid 13892,0
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decl (Decl
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n "clock"
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t "std_ulogic"
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)
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declText (MLText
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va (VaSet
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isHidden 1
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font "Verdana,8,0"
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)
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xt "2000,11400,15500,12400"
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st "SIGNAL clock : std_ulogic"
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)
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uid 13896,0
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decl (Decl
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n "reset"
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t "std_ulogic"
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suid 125,0
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)
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declText (MLText
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uid 13897,0
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va (VaSet
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isHidden 1
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font "Verdana,8,0"
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)
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xt "2000,14600,15500,15600"
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st "SIGNAL reset : std_ulogic"
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)
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)
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*43 (Net
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uid 13922,0
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decl (Decl
|
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n "lowpassInY"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 12
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suid 127,0
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)
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declText (MLText
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uid 13923,0
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va (VaSet
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isHidden 1
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)
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xt "0,0,33000,1200"
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st "SIGNAL lowpassInY : unsigned(signalBitNb-1 DOWNTO 0)"
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)
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)
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*44 (Net
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uid 13924,0
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decl (Decl
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n "lowpassOutY"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 13
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suid 128,0
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)
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declText (MLText
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uid 13925,0
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va (VaSet
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isHidden 1
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)
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xt "0,0,33500,1200"
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st "SIGNAL lowpassOutY : unsigned(signalBitNb-1 DOWNTO 0)"
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)
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)
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*45 (SaComponent
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uid 14527,0
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optionalChildren [
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*46 (CptPort
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uid 14471,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 14472,0
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ro 90
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va (VaSet
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vasetType 1
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|
fg "0,65535,0"
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)
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xt "68250,56625,69000,57375"
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)
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tg (CPTG
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|
uid 14473,0
|
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
|
|
uid 14474,0
|
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va (VaSet
|
|
)
|
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xt "70000,56400,73000,57600"
|
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st "hClk"
|
|
blo "70000,57400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hClk"
|
|
t "std_ulogic"
|
|
o 13
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*47 (CptPort
|
|
uid 14475,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14476,0
|
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ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,38625,69000,39375"
|
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)
|
|
tg (CPTG
|
|
uid 14477,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14478,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,38400,73700,39600"
|
|
st "hAddr"
|
|
blo "70000,39400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hAddr"
|
|
t "unsigned"
|
|
b "(ahbAddressBitNb-1 downto 0)"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*48 (CptPort
|
|
uid 14479,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14480,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "85000,38625,85750,39375"
|
|
)
|
|
tg (CPTG
|
|
uid 14481,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14482,0
|
|
va (VaSet
|
|
)
|
|
xt "81001,38400,84001,39600"
|
|
st "outX"
|
|
ju 2
|
|
blo "84001,39400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outX"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*49 (CptPort
|
|
uid 14483,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14484,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,58625,69000,59375"
|
|
)
|
|
tg (CPTG
|
|
uid 14485,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14486,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,58400,75400,59600"
|
|
st "hReset_n"
|
|
blo "70000,59400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hReset_n"
|
|
t "std_ulogic"
|
|
o 14
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*50 (CptPort
|
|
uid 14487,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14488,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "85000,40625,85750,41375"
|
|
)
|
|
tg (CPTG
|
|
uid 14489,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14490,0
|
|
va (VaSet
|
|
)
|
|
xt "81001,40400,84001,41600"
|
|
st "outY"
|
|
ju 2
|
|
blo "84001,41400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outY"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*51 (CptPort
|
|
uid 14491,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14492,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,40625,69000,41375"
|
|
)
|
|
tg (CPTG
|
|
uid 14493,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14494,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,40400,74600,41600"
|
|
st "hWData"
|
|
blo "70000,41400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hWData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 downto 0)"
|
|
o 4
|
|
suid 11,0
|
|
)
|
|
)
|
|
)
|
|
*52 (CptPort
|
|
uid 14495,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14496,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "85000,44625,85750,45375"
|
|
)
|
|
tg (CPTG
|
|
uid 14497,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14498,0
|
|
va (VaSet
|
|
)
|
|
xt "78201,44400,84001,45600"
|
|
st "selSinCos"
|
|
ju 2
|
|
blo "84001,45400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 13,0
|
|
)
|
|
)
|
|
)
|
|
*53 (CptPort
|
|
uid 14499,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14500,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "85000,56625,85750,57375"
|
|
)
|
|
tg (CPTG
|
|
uid 14501,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14502,0
|
|
va (VaSet
|
|
)
|
|
xt "79400,56400,84000,57600"
|
|
st "testOut"
|
|
ju 2
|
|
blo "84000,57400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "testOut"
|
|
t "std_ulogic_vector"
|
|
b "(1 TO testOutBitNb)"
|
|
o 6
|
|
suid 2014,0
|
|
)
|
|
)
|
|
)
|
|
*54 (CptPort
|
|
uid 14503,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14504,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,48625,69000,49375"
|
|
)
|
|
tg (CPTG
|
|
uid 14505,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14506,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,48400,74400,49600"
|
|
st "hRData"
|
|
blo "70000,49400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hRData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 downto 0)"
|
|
o 7
|
|
suid 2015,0
|
|
)
|
|
)
|
|
)
|
|
*55 (CptPort
|
|
uid 14507,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14508,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,42625,69000,43375"
|
|
)
|
|
tg (CPTG
|
|
uid 14509,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14510,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,42400,74200,43600"
|
|
st "hTrans"
|
|
blo "70000,43400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hTrans"
|
|
t "std_ulogic_vector"
|
|
b "(ahbTransBitNb-1 downto 0)"
|
|
o 8
|
|
suid 2016,0
|
|
)
|
|
)
|
|
)
|
|
*56 (CptPort
|
|
uid 14511,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14512,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,44625,69000,45375"
|
|
)
|
|
tg (CPTG
|
|
uid 14513,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14514,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,44400,73900,45600"
|
|
st "hWrite"
|
|
blo "70000,45400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hWrite"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 2017,0
|
|
)
|
|
)
|
|
)
|
|
*57 (CptPort
|
|
uid 14515,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14516,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,46625,69000,47375"
|
|
)
|
|
tg (CPTG
|
|
uid 14517,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14518,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,46400,72900,47600"
|
|
st "hSel"
|
|
blo "70000,47400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hSel"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 2018,0
|
|
)
|
|
)
|
|
)
|
|
*58 (CptPort
|
|
uid 14519,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14520,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,50625,69000,51375"
|
|
)
|
|
tg (CPTG
|
|
uid 14521,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14522,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,50400,74400,51600"
|
|
st "hReady"
|
|
blo "70000,51400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hReady"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 2019,0
|
|
)
|
|
)
|
|
)
|
|
*59 (CptPort
|
|
uid 14523,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 14524,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "68250,52625,69000,53375"
|
|
)
|
|
tg (CPTG
|
|
uid 14525,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 14526,0
|
|
va (VaSet
|
|
)
|
|
xt "70000,52400,73800,53600"
|
|
st "hResp"
|
|
blo "70000,53400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hResp"
|
|
t "std_ulogic"
|
|
o 12
|
|
suid 2020,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 14528,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "69000,35000,85000,61000"
|
|
)
|
|
oxt "43000,6000,59000,32000"
|
|
ttg (MlTextGroup
|
|
uid 14529,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*60 (Text
|
|
uid 14530,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "69600,60800,78000,62000"
|
|
st "SystemOnChip"
|
|
blo "69600,61800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*61 (Text
|
|
uid 14531,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "69600,61700,75800,62900"
|
|
st "ahbBeamer"
|
|
blo "69600,62700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*62 (Text
|
|
uid 14532,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "69600,62600,73300,63800"
|
|
st "I_DUT"
|
|
blo "69600,63600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 14533,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 14534,0
|
|
text (MLText
|
|
uid 14535,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "69000,64600,94800,66600"
|
|
st "patternAddressBitNb = patternAddressBitNb ( positive )
|
|
testOutBitNb = testOutBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "patternAddressBitNb"
|
|
type "positive"
|
|
value "patternAddressBitNb"
|
|
)
|
|
(GiElement
|
|
name "testOutBitNb"
|
|
type "positive"
|
|
value "testOutBitNb"
|
|
)
|
|
]
|
|
)
|
|
viewicon (ZoomableIcon
|
|
uid 14536,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "49152,49152,49152"
|
|
)
|
|
xt "69250,59250,70750,60750"
|
|
iconName "BlockDiagram.png"
|
|
iconMaskName "BlockDiagram.msk"
|
|
ftype 1
|
|
)
|
|
ordering 1
|
|
viewiconposition 0
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*63 (Wire
|
|
uid 12557,0
|
|
shape (OrthoPolyLine
|
|
uid 12558,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "67000,59000,68250,69000"
|
|
pts [
|
|
"68250,59000"
|
|
"67000,59000"
|
|
"67000,69000"
|
|
]
|
|
)
|
|
start &49
|
|
end &22
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12561,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12562,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "60250,57600,67050,59000"
|
|
st "hReset_n"
|
|
blo "60250,58800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &12
|
|
)
|
|
*64 (Wire
|
|
uid 12565,0
|
|
shape (OrthoPolyLine
|
|
uid 12566,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65000,57000,68250,69000"
|
|
pts [
|
|
"68250,57000"
|
|
"65000,57000"
|
|
"65000,69000"
|
|
]
|
|
)
|
|
start &46
|
|
end &22
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12569,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12570,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63250,55600,66750,57000"
|
|
st "hClk"
|
|
blo "63250,56800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &13
|
|
)
|
|
*65 (Wire
|
|
uid 12573,0
|
|
shape (OrthoPolyLine
|
|
uid 12574,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61000,53000,68250,69000"
|
|
pts [
|
|
"68250,53000"
|
|
"61000,53000"
|
|
"61000,69000"
|
|
]
|
|
)
|
|
start &59
|
|
end &22
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12577,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12578,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "62250,51600,66950,53000"
|
|
st "hResp"
|
|
blo "62250,52800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &14
|
|
)
|
|
*66 (Wire
|
|
uid 12581,0
|
|
shape (OrthoPolyLine
|
|
uid 12582,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "59000,51000,68250,69000"
|
|
pts [
|
|
"68250,51000"
|
|
"59000,51000"
|
|
"59000,69000"
|
|
]
|
|
)
|
|
start &58
|
|
end &22
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12585,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12586,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "61250,49600,66750,51000"
|
|
st "hReady"
|
|
blo "61250,50800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &15
|
|
)
|
|
*67 (Wire
|
|
uid 12589,0
|
|
shape (OrthoPolyLine
|
|
uid 12590,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "57000,49000,68250,69000"
|
|
pts [
|
|
"68250,49000"
|
|
"57000,49000"
|
|
"57000,69000"
|
|
]
|
|
)
|
|
start &54
|
|
end &22
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12593,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12594,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "62250,47600,67650,49000"
|
|
st "hRData"
|
|
blo "62250,48800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*68 (Wire
|
|
uid 12597,0
|
|
shape (OrthoPolyLine
|
|
uid 12598,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "55000,47000,68250,69000"
|
|
pts [
|
|
"68250,47000"
|
|
"55000,47000"
|
|
"55000,69000"
|
|
]
|
|
)
|
|
start &57
|
|
end &22
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12601,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12602,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63250,45600,66750,47000"
|
|
st "hSel"
|
|
blo "63250,46800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*69 (Wire
|
|
uid 12605,0
|
|
shape (OrthoPolyLine
|
|
uid 12606,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "53000,45000,68250,69000"
|
|
pts [
|
|
"68250,45000"
|
|
"53000,45000"
|
|
"53000,69000"
|
|
]
|
|
)
|
|
start &56
|
|
end &22
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12609,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12610,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "62250,43600,67250,45000"
|
|
st "hWrite"
|
|
blo "62250,44800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &18
|
|
)
|
|
*70 (Wire
|
|
uid 12613,0
|
|
shape (OrthoPolyLine
|
|
uid 12614,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "51000,43000,68250,69000"
|
|
pts [
|
|
"68250,43000"
|
|
"51000,43000"
|
|
"51000,69000"
|
|
]
|
|
)
|
|
start &55
|
|
end &22
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12617,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12618,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "62250,41600,67350,43000"
|
|
st "hTrans"
|
|
blo "62250,42800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*71 (Wire
|
|
uid 12621,0
|
|
shape (OrthoPolyLine
|
|
uid 12622,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "49000,41000,68250,69000"
|
|
pts [
|
|
"68250,41000"
|
|
"49000,41000"
|
|
"49000,69000"
|
|
]
|
|
)
|
|
start &51
|
|
end &22
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12625,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12626,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "61250,39600,67150,41000"
|
|
st "hWData"
|
|
blo "61250,40800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &20
|
|
)
|
|
*72 (Wire
|
|
uid 12629,0
|
|
shape (OrthoPolyLine
|
|
uid 12630,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "47000,39000,68250,69000"
|
|
pts [
|
|
"68250,39000"
|
|
"47000,39000"
|
|
"47000,69000"
|
|
]
|
|
)
|
|
start &47
|
|
end &22
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 12633,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 12634,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "62250,37600,66750,39000"
|
|
st "hAddr"
|
|
blo "62250,38800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &21
|
|
)
|
|
*73 (Wire
|
|
uid 13631,0
|
|
shape (OrthoPolyLine
|
|
uid 13632,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "85750,45000,89000,69000"
|
|
pts [
|
|
"85750,45000"
|
|
"89000,45000"
|
|
"89000,69000"
|
|
]
|
|
)
|
|
start &52
|
|
end &22
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 13635,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 13636,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "87750,43600,94650,45000"
|
|
st "selSinCos"
|
|
blo "87750,44800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &26
|
|
)
|
|
*74 (Wire
|
|
uid 13639,0
|
|
optionalChildren [
|
|
*75 (BdJunction
|
|
uid 13904,0
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
uid 13905,0
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "92600,40600,93400,41400"
|
|
radius 400
|
|
)
|
|
)
|
|
]
|
|
shape (OrthoPolyLine
|
|
uid 13640,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "85750,41000,93000,69000"
|
|
pts [
|
|
"85750,41000"
|
|
"93000,41000"
|
|
"93000,69000"
|
|
]
|
|
)
|
|
start &50
|
|
end &22
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 13643,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 13644,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "87750,39600,91350,41000"
|
|
st "outY"
|
|
blo "87750,40800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &27
|
|
)
|
|
*76 (Wire
|
|
uid 13647,0
|
|
shape (OrthoPolyLine
|
|
uid 13648,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "85750,39000,95000,69000"
|
|
pts [
|
|
"85750,39000"
|
|
"95000,39000"
|
|
"95000,69000"
|
|
]
|
|
)
|
|
start &48
|
|
end &22
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 13651,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 13652,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "87750,37600,91450,39000"
|
|
st "outX"
|
|
blo "87750,38800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &28
|
|
)
|
|
*77 (Wire
|
|
uid 13874,0
|
|
shape (OrthoPolyLine
|
|
uid 13875,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "97000,31000,100250,41000"
|
|
pts [
|
|
"100250,41000"
|
|
"97000,41000"
|
|
"97000,31000"
|
|
]
|
|
)
|
|
start &37
|
|
end &29
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 13878,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 13879,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "94000,39600,102800,41000"
|
|
st "lowpassInY"
|
|
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archName ""
|
|
archPath ""
|
|
)
|
|
defaultVerilogComponent (VerilogComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "-2100,0,10100,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*104 (Text
|
|
va (VaSet
|
|
)
|
|
xt "-1600,2550,2800,3750"
|
|
st "Library"
|
|
blo "-1600,3550"
|
|
)
|
|
*105 (Text
|
|
va (VaSet
|
|
)
|
|
xt "-1600,3750,10100,4950"
|
|
st "VerilogComponent"
|
|
blo "-1600,4750"
|
|
)
|
|
*106 (Text
|
|
va (VaSet
|
|
)
|
|
xt "-1600,4950,1200,6150"
|
|
st "U_0"
|
|
blo "-1600,5950"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "-8600,550,-8600,550"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,37120"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*107 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "2950,3400,5250,4400"
|
|
st "eb1"
|
|
blo "2950,4200"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*108 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "2950,4400,4150,5400"
|
|
st "1"
|
|
blo "2950,5200"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
viewicon (ZoomableIcon
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "49152,49152,49152"
|
|
)
|
|
xt "250,8250,1750,9750"
|
|
iconName "UnknownFile.png"
|
|
iconMaskName "UnknownFile.msk"
|
|
)
|
|
viewiconposition 0
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
)
|
|
xt "-750,-600,750,600"
|
|
st "G"
|
|
blo "-750,400"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "-2875,-375,-2875,-375"
|
|
ju 2
|
|
blo "-2875,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "2875,-375,2875,-375"
|
|
blo "2875,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "3000,500,3000,500"
|
|
blo "3000,500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "3000,500,3000,500"
|
|
blo "3000,500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3400,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,4700,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineColor "32768,0,0"
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,400,3700,1400"
|
|
st "bundle0"
|
|
blo "0,1200"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1400,1500,2600"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1200,9600,2400"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1400,18500,-200"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1750"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "150,400,950,1400"
|
|
st "1"
|
|
blo "150,1200"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*109 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "11800,20000,21800,21000"
|
|
st "Frame Declarations"
|
|
blo "11800,20800"
|
|
)
|
|
*110 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11800,21000,11800,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1400,11000,-200"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1750"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "150,400,950,1400"
|
|
st "1"
|
|
blo "150,1200"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*111 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "11800,20000,21800,21000"
|
|
st "Frame Declarations"
|
|
blo "11800,20800"
|
|
)
|
|
*112 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11800,21000,11800,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "29000,26800,36000,27800"
|
|
st "Declarations"
|
|
blo "29000,27600"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "29000,28000,32400,29000"
|
|
st "Ports:"
|
|
blo "29000,28800"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "29000,27800,33800,28800"
|
|
st "Pre User:"
|
|
blo "29000,28600"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
)
|
|
xt "31000,28800,56600,37200"
|
|
st "constant patternAddressBitNb: positive := 9;
|
|
constant testOutBitNb: positive := 16;
|
|
|
|
constant signalBitNb: positive := 16;
|
|
constant lowpassShiftBitNb: positive := 8;
|
|
constant clockFrequency : real := 60.0E6;
|
|
--constant clockFrequency : real := 66.0E6;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "29000,28000,38000,29000"
|
|
st "Diagram Signals:"
|
|
blo "29000,28800"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "29000,28000,35000,29000"
|
|
st "Post User:"
|
|
blo "29000,28800"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "31000,42400,31000,42400"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 129,0
|
|
usingSuid 1
|
|
emptyRow *113 (LEmptyRow
|
|
)
|
|
uid 3310,0
|
|
optionalChildren [
|
|
*114 (RefLabelRowHdr
|
|
)
|
|
*115 (TitleRowHdr
|
|
)
|
|
*116 (FilterRowHdr
|
|
)
|
|
*117 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*118 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*119 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*120 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*121 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*122 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*123 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*124 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*125 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*126 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hReset_n"
|
|
t "std_uLogic"
|
|
o 6
|
|
suid 108,0
|
|
)
|
|
)
|
|
uid 12637,0
|
|
)
|
|
*127 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hClk"
|
|
t "std_uLogic"
|
|
o 3
|
|
suid 109,0
|
|
)
|
|
)
|
|
uid 12639,0
|
|
)
|
|
*128 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hResp"
|
|
t "std_uLogic"
|
|
o 7
|
|
suid 110,0
|
|
)
|
|
)
|
|
uid 12641,0
|
|
)
|
|
*129 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hReady"
|
|
t "std_uLogic"
|
|
o 5
|
|
suid 111,0
|
|
)
|
|
)
|
|
uid 12643,0
|
|
)
|
|
*130 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hRData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 112,0
|
|
)
|
|
)
|
|
uid 12645,0
|
|
)
|
|
*131 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hSel"
|
|
t "std_uLogic"
|
|
o 8
|
|
suid 113,0
|
|
)
|
|
)
|
|
uid 12647,0
|
|
)
|
|
*132 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hWrite"
|
|
t "std_uLogic"
|
|
o 11
|
|
suid 114,0
|
|
)
|
|
)
|
|
uid 12649,0
|
|
)
|
|
*133 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hTrans"
|
|
t "std_ulogic_vector"
|
|
b "(ahbTransBitNb-1 DOWNTO 0)"
|
|
o 9
|
|
suid 115,0
|
|
)
|
|
)
|
|
uid 12651,0
|
|
)
|
|
*134 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hWData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 DOWNTO 0)"
|
|
o 10
|
|
suid 116,0
|
|
)
|
|
)
|
|
uid 12653,0
|
|
)
|
|
*135 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "hAddr"
|
|
t "unsigned"
|
|
b "( ahbAddressBitNb-1 DOWNTO 0 )"
|
|
o 2
|
|
suid 117,0
|
|
)
|
|
)
|
|
uid 12655,0
|
|
)
|
|
*136 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 17
|
|
suid 120,0
|
|
)
|
|
)
|
|
uid 13653,0
|
|
)
|
|
*137 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "outY"
|
|
t "std_ulogic"
|
|
o 15
|
|
suid 121,0
|
|
)
|
|
)
|
|
uid 13655,0
|
|
)
|
|
*138 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "outX"
|
|
t "std_ulogic"
|
|
o 14
|
|
suid 122,0
|
|
)
|
|
)
|
|
uid 13657,0
|
|
)
|
|
*139 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 123,0
|
|
)
|
|
)
|
|
uid 13914,0
|
|
)
|
|
*140 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 16
|
|
suid 125,0
|
|
)
|
|
)
|
|
uid 13918,0
|
|
)
|
|
*141 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "lowpassInY"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 12
|
|
suid 127,0
|
|
)
|
|
)
|
|
uid 13926,0
|
|
)
|
|
*142 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "lowpassOutY"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 13
|
|
suid 128,0
|
|
)
|
|
)
|
|
uid 13928,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 3323,0
|
|
optionalChildren [
|
|
*143 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *144 (MRCItem
|
|
litem &113
|
|
pos 17
|
|
dimension 20
|
|
)
|
|
uid 3325,0
|
|
optionalChildren [
|
|
*145 (MRCItem
|
|
litem &114
|
|
pos 0
|
|
dimension 20
|
|
uid 3326,0
|
|
)
|
|
*146 (MRCItem
|
|
litem &115
|
|
pos 1
|
|
dimension 23
|
|
uid 3327,0
|
|
)
|
|
*147 (MRCItem
|
|
litem &116
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 3328,0
|
|
)
|
|
*148 (MRCItem
|
|
litem &126
|
|
pos 0
|
|
dimension 20
|
|
uid 12638,0
|
|
)
|
|
*149 (MRCItem
|
|
litem &127
|
|
pos 1
|
|
dimension 20
|
|
uid 12640,0
|
|
)
|
|
*150 (MRCItem
|
|
litem &128
|
|
pos 2
|
|
dimension 20
|
|
uid 12642,0
|
|
)
|
|
*151 (MRCItem
|
|
litem &129
|
|
pos 3
|
|
dimension 20
|
|
uid 12644,0
|
|
)
|
|
*152 (MRCItem
|
|
litem &130
|
|
pos 4
|
|
dimension 20
|
|
uid 12646,0
|
|
)
|
|
*153 (MRCItem
|
|
litem &131
|
|
pos 5
|
|
dimension 20
|
|
uid 12648,0
|
|
)
|
|
*154 (MRCItem
|
|
litem &132
|
|
pos 6
|
|
dimension 20
|
|
uid 12650,0
|
|
)
|
|
*155 (MRCItem
|
|
litem &133
|
|
pos 7
|
|
dimension 20
|
|
uid 12652,0
|
|
)
|
|
*156 (MRCItem
|
|
litem &134
|
|
pos 8
|
|
dimension 20
|
|
uid 12654,0
|
|
)
|
|
*157 (MRCItem
|
|
litem &135
|
|
pos 9
|
|
dimension 20
|
|
uid 12656,0
|
|
)
|
|
*158 (MRCItem
|
|
litem &136
|
|
pos 10
|
|
dimension 20
|
|
uid 13654,0
|
|
)
|
|
*159 (MRCItem
|
|
litem &137
|
|
pos 11
|
|
dimension 20
|
|
uid 13656,0
|
|
)
|
|
*160 (MRCItem
|
|
litem &138
|
|
pos 12
|
|
dimension 20
|
|
uid 13658,0
|
|
)
|
|
*161 (MRCItem
|
|
litem &139
|
|
pos 13
|
|
dimension 20
|
|
uid 13915,0
|
|
)
|
|
*162 (MRCItem
|
|
litem &140
|
|
pos 14
|
|
dimension 20
|
|
uid 13919,0
|
|
)
|
|
*163 (MRCItem
|
|
litem &141
|
|
pos 15
|
|
dimension 20
|
|
uid 13927,0
|
|
)
|
|
*164 (MRCItem
|
|
litem &142
|
|
pos 16
|
|
dimension 20
|
|
uid 13929,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 3329,0
|
|
optionalChildren [
|
|
*165 (MRCItem
|
|
litem &117
|
|
pos 0
|
|
dimension 20
|
|
uid 3330,0
|
|
)
|
|
*166 (MRCItem
|
|
litem &119
|
|
pos 1
|
|
dimension 50
|
|
uid 3331,0
|
|
)
|
|
*167 (MRCItem
|
|
litem &120
|
|
pos 2
|
|
dimension 100
|
|
uid 3332,0
|
|
)
|
|
*168 (MRCItem
|
|
litem &121
|
|
pos 3
|
|
dimension 50
|
|
uid 3333,0
|
|
)
|
|
*169 (MRCItem
|
|
litem &122
|
|
pos 4
|
|
dimension 100
|
|
uid 3334,0
|
|
)
|
|
*170 (MRCItem
|
|
litem &123
|
|
pos 5
|
|
dimension 100
|
|
uid 3335,0
|
|
)
|
|
*171 (MRCItem
|
|
litem &124
|
|
pos 6
|
|
dimension 50
|
|
uid 3336,0
|
|
)
|
|
*172 (MRCItem
|
|
litem &125
|
|
pos 7
|
|
dimension 80
|
|
uid 3337,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 3324,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 3309,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *173 (LEmptyRow
|
|
)
|
|
uid 3339,0
|
|
optionalChildren [
|
|
*174 (RefLabelRowHdr
|
|
)
|
|
*175 (TitleRowHdr
|
|
)
|
|
*176 (FilterRowHdr
|
|
)
|
|
*177 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*178 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*179 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*180 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*181 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*182 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*183 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*184 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 3351,0
|
|
optionalChildren [
|
|
*185 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *186 (MRCItem
|
|
litem &173
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 3353,0
|
|
optionalChildren [
|
|
*187 (MRCItem
|
|
litem &174
|
|
pos 0
|
|
dimension 20
|
|
uid 3354,0
|
|
)
|
|
*188 (MRCItem
|
|
litem &175
|
|
pos 1
|
|
dimension 23
|
|
uid 3355,0
|
|
)
|
|
*189 (MRCItem
|
|
litem &176
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 3356,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 3357,0
|
|
optionalChildren [
|
|
*190 (MRCItem
|
|
litem &177
|
|
pos 0
|
|
dimension 20
|
|
uid 3358,0
|
|
)
|
|
*191 (MRCItem
|
|
litem &179
|
|
pos 1
|
|
dimension 50
|
|
uid 3359,0
|
|
)
|
|
*192 (MRCItem
|
|
litem &180
|
|
pos 2
|
|
dimension 100
|
|
uid 3360,0
|
|
)
|
|
*193 (MRCItem
|
|
litem &181
|
|
pos 3
|
|
dimension 100
|
|
uid 3361,0
|
|
)
|
|
*194 (MRCItem
|
|
litem &182
|
|
pos 4
|
|
dimension 50
|
|
uid 3362,0
|
|
)
|
|
*195 (MRCItem
|
|
litem &183
|
|
pos 5
|
|
dimension 50
|
|
uid 3363,0
|
|
)
|
|
*196 (MRCItem
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litem &184
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pos 6
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dimension 80
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uid 3364,0
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)
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]
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)
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fixedCol 3
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fixedRow 2
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name "Ports"
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uid 3352,0
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vaOverrides [
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]
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)
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]
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)
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uid 3338,0
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type 1
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)
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activeModelName "BlockDiag"
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)
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