7 lines
		
	
	
		
			174 B
		
	
	
	
		
			VHDL
		
	
	
	
	
	
			
		
		
	
	
			7 lines
		
	
	
		
			174 B
		
	
	
	
		
			VHDL
		
	
	
	
	
	
ARCHITECTURE studentVersion OF periphControlReg IS
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BEGIN
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  run               <= '0';
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  updatePattern     <= '0';
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  interpolateLinear <= '0';
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END ARCHITECTURE studentVersion;
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