117 lines
3.0 KiB
VHDL
117 lines
3.0 KiB
VHDL
LIBRARY std;
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USE std.textio.ALL;
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LIBRARY ieee;
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USE ieee.std_logic_textio.ALL;
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LIBRARY Common_test;
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USE Common_test.testutils.all;
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ARCHITECTURE rtl OF heirv32_sc_tester IS
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constant clockPeriod : time := 1.0/66E6 * 1 sec;
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signal sClock : std_uLogic := '1';
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signal sReset : std_uLogic ;
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signal testInfo : string(1 to 40) := (others => ' ');
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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sReset <= '1', '0' after 3.5*clockPeriod;
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rst <= sReset;
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sClock <= not sClock after clockPeriod/2;
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clk <= transport sClock after 0.9*clockPeriod;
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btns <= (others => '0');
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process
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-- Wait list
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-- 1 for all
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begin
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en <= '0';
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testInfo <= pad("Wait reset", testInfo'length);
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wait until rst = '0';
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while true loop
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en <= '1';
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testInfo <= pad("Addi, addr. 00", testInfo'length);
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wait until clk'event and clk = '1';
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wait for clockPeriod;
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testInfo <= pad("Addi, addr. 04", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Addi, addr. 08", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Or, addr. 0C", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("And, addr. 10", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Add, addr. 14", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Beq, addr. 18", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Slt, addr. 1C", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Beq, addr. 20", testInfo'length);
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wait for clockPeriod;
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--testInfo <= pad("Addi, addr. 24", testInfo'length);
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--wait for clockPeriod;
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testInfo <= pad("Slt, addr. 28", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Add, addr. 2C", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Sub, addr. 30", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Sw, addr. 34", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Lw, addr. 38", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Add, addr. 3C", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Jal, addr. 40", testInfo'length);
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wait for clockPeriod;
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--testInfo <= pad("Addi, addr. 44", testInfo'length);
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--wait for clockPeriod;
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testInfo <= pad("Add, addr. 48", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Sw, addr.4C", testInfo'length);
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wait for clockPeriod;
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testInfo <= pad("Beq, addr. 50", testInfo'length);
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wait for 0.8*clockPeriod;
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en <= '0';
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testInfo <= pad("Wait a bit, PC should be 0", testInfo'length);
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wait for 9.2*clockPeriod;
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testInfo <= pad("Enabling system", testInfo'length);
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en <= '1';
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wait until clk'event and clk = '1';
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end loop;
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end process;
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END ARCHITECTURE rtl;
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