62 lines
1.7 KiB
VHDL
62 lines
1.7 KiB
VHDL
library Common;
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use Common.CommonLib.all;
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ARCHITECTURE studentVersion OF unitCounter IS
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signal unitCounter: unsigned(requiredBitNb(unitCountDivide)-1 downto 0);
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signal unitCountDone: std_ulogic;
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signal unitNbCounter: unsigned(unitnB'range);
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signal unitNbCountDone: std_ulogic;
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BEGIN
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-- count unit base period
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countUnitDuration: process(reset, clock)
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begin
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if reset = '1' then
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unitCounter <= (others => '0');
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elsif rising_edge(clock) then
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if unitCounter = 0 then
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if (startCounter = '1') or (unitNbCounter > 0) then
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unitCounter <= unitCounter + 1;
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end if;
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else
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if unitCountDone = '0' then
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unitCounter <= unitCounter + 1;
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else
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unitCounter <= (others => '0');
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end if;
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end if;
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end if;
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end process countUnitDuration;
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unitCountDone <= '1' when unitCounter = unitCountDivide
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else '0';
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-- count unit period number
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countPeriods: process(reset, clock)
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begin
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if reset = '1' then
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unitNbCounter <= (others => '0');
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elsif rising_edge(clock) then
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if unitNbCounter = 0 then
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if startCounter = '1' then
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unitNbCounter <= unitNbCounter + 1;
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end if;
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else
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if unitNbCountDone = '0' then
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if unitCountDone = '1' then
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unitNbCounter <= unitNbCounter + 1;
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end if;
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else
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unitNbCounter <= (others => '0');
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end if;
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end if;
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end if;
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end process countPeriods;
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unitNbCountDone <= '1' when (unitNbCounter = unitNb) and (unitCountDone = '1')
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else '0';
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done <= unitNbCountDone;
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END ARCHITECTURE studentVersion;
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