29 lines
796 B
VHDL
29 lines
796 B
VHDL
library Common;
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use Common.CommonLib.all;
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ARCHITECTURE studentVersion OF toneGenerator IS
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constant toneCounterBitNb: positive := requiredBitNb(toneDivide-1);
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signal toneCounter: unsigned(toneCounterBitNb-1 downto 0);
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constant toneMin : natural := (2**toneCounterBitNb - toneDivide) / 2;
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constant toneMax : natural := toneMin + toneDivide;
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BEGIN
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divide: process(reset, clock)
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begin
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if reset = '1' then
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toneCounter <= to_unsigned(toneMin, toneCounter'length);
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elsif rising_edge(clock) then
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if toneCounter = toneMax then
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toneCounter <= to_unsigned(toneMin, toneCounter'length);
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else
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toneCounter <= toneCounter + 1;
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end if;
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end if;
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end process divide;
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tone <= toneCounter(toneCounter'high);
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END ARCHITECTURE studentVersion;
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