30 lines
511 B
VHDL
30 lines
511 B
VHDL
ARCHITECTURE studentVersion OF interpolatorTrigger IS
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signal counter : unsigned(counterBitNb-1 downto 0);
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BEGIN
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process(clock, reset)
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begin
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if reset = '1' then
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counter <= (others => '0');
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elsif rising_edge(clock) then
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if en = '1' then
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counter <= counter - 1;
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end if;
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end if;
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end process;
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process(counter)
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begin
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if counter = 0 then
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triggerOut <= '1';
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else
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triggerOut <= '0';
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end if;
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end process;
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END ARCHITECTURE studentVersion;
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