18 lines
493 B
VHDL
18 lines
493 B
VHDL
ARCHITECTURE studentVersion OF lowpass IS
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signal accumulator: unsigned((signalBitNb-1)+shiftBitNb downto 0);
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BEGIN
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process(clock)
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begin
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if reset = '1' then
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accumulator <= (others => '0');
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elsif rising_edge(clock) then
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accumulator <= accumulator + resize(lowpassIn,signalBitNb+shiftBitNb) - shift_right(accumulator, shiftBitNb);
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end if;
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end process;
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lowpassOut <= resize(shift_right(accumulator, shiftBitNb), signalBitNb);
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END ARCHITECTURE studentVersion;
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