33 lines
799 B
Plaintext
33 lines
799 B
Plaintext
-- VHDL Entity Memory.FIFO_bram.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:45:15 08/28/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY FIFO_bram IS
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GENERIC(
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dataBitNb : positive := 8;
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depth : positive := 8
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);
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PORT(
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write : IN std_ulogic;
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0);
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read : IN std_ulogic;
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dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0);
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empty : OUT std_ulogic;
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full : OUT std_ulogic
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);
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-- Declarations
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END FIFO_bram ;
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