155 lines
4.4 KiB
Plaintext
155 lines
4.4 KiB
Plaintext
--
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-- VHDL Architecture Morse.morseEncoder.struct
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 14:50:20 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY Memory;
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LIBRARY Morse;
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LIBRARY RS232;
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ARCHITECTURE struct OF morseEncoder IS
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-- Architecture declarations
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constant fifoDepth : positive := 100;
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-- Internal signal declarations
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SIGNAL characterReg : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0);
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SIGNAL characterIn : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0);
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SIGNAL characterValid : std_ulogic;
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SIGNAL morseOut : std_ulogic;
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SIGNAL tone : std_ulogic;
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SIGNAL charNotReady : std_ulogic;
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SIGNAL readChar : std_ulogic;
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-- Component Declarations
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COMPONENT FIFO_bram
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GENERIC (
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dataBitNb : positive := 8;
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depth : positive := 8
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);
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PORT (
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write : IN std_ulogic ;
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0);
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read : IN std_ulogic ;
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dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0);
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empty : OUT std_ulogic ;
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full : OUT std_ulogic
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);
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END COMPONENT;
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COMPONENT charToMorse
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GENERIC (
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characterBitNb : positive := 8;
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unitCountDivide : positive := 10E3
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);
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PORT (
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morseOut : OUT std_ulogic ;
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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charIn : IN std_ulogic_vector (characterBitNb-1 DOWNTO 0);
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readChar : OUT std_ulogic ;
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charNotReady : IN std_ulogic
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);
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END COMPONENT;
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COMPONENT toneGenerator
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GENERIC (
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toneDivide : positive := 100E3
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);
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PORT (
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tone : OUT std_ulogic ;
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clock : IN std_ulogic ;
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reset : IN std_ulogic
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);
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END COMPONENT;
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COMPONENT serialPortReceiver
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GENERIC (
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dataBitNb : positive := 8;
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baudRateDivide : positive := 2083
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);
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PORT (
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RxD : IN std_ulogic ;
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0);
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dataValid : OUT std_ulogic
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : FIFO_bram USE ENTITY Memory.FIFO_bram;
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FOR ALL : charToMorse USE ENTITY Morse.charToMorse;
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FOR ALL : serialPortReceiver USE ENTITY RS232.serialPortReceiver;
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FOR ALL : toneGenerator USE ENTITY Morse.toneGenerator;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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morseCode <= morseOut and tone;
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-- Instance port mappings.
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I_FIFO : FIFO_bram
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GENERIC MAP (
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dataBitNb => uartDataBitNb,
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depth => fifoDepth
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)
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PORT MAP (
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write => characterValid,
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clock => clock,
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reset => reset,
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dataOut => characterReg,
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read => readChar,
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dataIn => characterIn,
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empty => charNotReady,
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full => OPEN
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);
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I_enc : charToMorse
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GENERIC MAP (
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characterBitNb => uartDataBitNb,
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unitCountDivide => integer(clockFrequency*unitDuration + 0.5)
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)
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PORT MAP (
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morseOut => morseOut,
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clock => clock,
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reset => reset,
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charNotReady => charNotReady,
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charIn => characterReg,
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readChar => readChar
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);
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I_tone : toneGenerator
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GENERIC MAP (
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toneDivide => integer(clockFrequency/toneFrequency + 0.5)
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)
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PORT MAP (
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tone => tone,
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clock => clock,
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reset => reset
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);
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I_UART : serialPortReceiver
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GENERIC MAP (
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dataBitNb => uartDataBitNb,
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baudRateDivide => integer(clockFrequency/uartBaudRate + 0.5)
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)
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PORT MAP (
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RxD => RxD,
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clock => clock,
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reset => reset,
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dataOut => characterIn,
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dataValid => characterValid
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);
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END struct;
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