28 lines
629 B
Plaintext
28 lines
629 B
Plaintext
-- VHDL Entity SplineInterpolator.sineTable.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:46 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY sineTable IS
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GENERIC(
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inputBitNb : positive := 16;
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outputBitNb : positive := 16;
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tableAddressBitNb : positive := 3
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);
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PORT(
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sine : OUT signed (outputBitNb-1 DOWNTO 0);
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phase : IN unsigned (inputBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END sineTable ;
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