1257 lines
16 KiB
Plaintext
1257 lines
16 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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version "26.1"
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litem &12
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tm "GenericEolColHdrMgr"
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font "courier,10,0"
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litem &27
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litem &29
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litem &34
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pos 2
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litem &35
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pos 3
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dimension 100
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uid 99,0
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litem &36
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pos 4
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dimension 50
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uid 101,0
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litem &37
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pos 5
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dimension 50
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uid 103,0
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*50 (MRCItem
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litem &38
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pos 6
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dimension 80
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uid 105,0
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fixedCol 3
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fixedRow 2
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name "Ports"
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uid 81,0
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vaOverrides [
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uid 109,0
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type 1
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
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)
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(vvPair
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variable "HDSDir"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tb/symbol.sb.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tb/symbol.sb.user"
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)
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(vvPair
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variable "SourceDir"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
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(vvPair
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variable "appl"
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value "HDL Designer"
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(vvPair
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variable "arch_name"
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value "symbol"
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(vvPair
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variable "concat_file"
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value "concatenated"
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(vvPair
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variable "config"
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value "%(unit)_%(view)_config"
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(vvPair
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variable "d"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tb"
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)
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(vvPair
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variable "d_logical"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tb"
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(vvPair
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variable "date"
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value "08/28/19"
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variable "day"
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value "Wed"
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variable "day_long"
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value "Wednesday"
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(vvPair
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variable "dd"
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value "28"
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(vvPair
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variable "entity_name"
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value "flash_tb"
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(vvPair
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variable "ext"
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value "<TBD>"
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)
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(vvPair
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variable "f"
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value "symbol.sb"
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)
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(vvPair
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variable "f_logical"
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value "symbol.sb"
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(vvPair
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variable "f_noext"
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value "symbol"
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(vvPair
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variable "graphical_source_author"
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value "francois"
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(vvPair
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variable "graphical_source_date"
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value "08/28/19"
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(vvPair
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variable "graphical_source_group"
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value "francois"
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(vvPair
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variable "graphical_source_host"
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value "Aphelia"
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(vvPair
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variable "graphical_source_time"
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value "13:45:27"
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(vvPair
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variable "group"
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value "francois"
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(vvPair
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variable "host"
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value "Aphelia"
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(vvPair
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variable "language"
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value "VHDL"
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(vvPair
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variable "library"
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value "Memory_test"
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)
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(vvPair
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variable "library_downstream_ModelSim"
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value "D:\\Users\\SysLo\\Master\\VHDL_comp"
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(vvPair
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variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/Libs/Memory_test/work"
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(vvPair
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variable "mm"
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value "08"
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(vvPair
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variable "module_name"
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value "flash_tb"
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(vvPair
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variable "month"
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value "Aug"
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)
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(vvPair
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variable "month_long"
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value "August"
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(vvPair
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variable "p"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tb/symbol.sb"
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)
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(vvPair
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variable "p_logical"
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tb/symbol.sb"
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)
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(vvPair
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variable "package_name"
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value "<Undefined Variable>"
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)
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(vvPair
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variable "project_name"
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value "hds"
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)
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(vvPair
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variable "series"
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value "HDL Designer Series"
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(vvPair
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variable "task_DesignCompilerPath"
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value "<TBD>"
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variable "task_LeonardoPath"
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value "<TBD>"
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variable "task_ModelSimPath"
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value "c:\\eda\\modelsim\\win32"
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variable "task_NC-SimPath"
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value "<TBD>"
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variable "task_PrecisionRTLPath"
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value "<TBD>"
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(vvPair
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variable "task_QuestaSimPath"
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value "<TBD>"
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(vvPair
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variable "task_VCSPath"
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value "<TBD>"
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variable "this_ext"
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value "sb"
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variable "this_file"
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value "symbol"
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variable "this_file_logical"
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value "symbol"
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(vvPair
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variable "time"
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value "13:45:27"
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(vvPair
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variable "unit"
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value "flash_tb"
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(vvPair
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variable "user"
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value "francois"
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variable "version"
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value "2018.1 (Build 12)"
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variable "view"
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value "symbol"
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variable "year"
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value "2019"
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(vvPair
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variable "yy"
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value "19"
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LanguageMgr "Vhdl2008LangMgr"
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uid 51,0
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