1607 lines
20 KiB
Plaintext
1607 lines
20 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 13,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 81,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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|
*4 (FilterRowHdr
|
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)
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|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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|
*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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|
*7 (GroupColHdr
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|
tm "GroupColHdrMgr"
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|
)
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|
*8 (NameColHdr
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|
tm "NameColHdrMgr"
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|
)
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|
*9 (ModeColHdr
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|
tm "ModeColHdrMgr"
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|
)
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|
*10 (TypeColHdr
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|
tm "TypeColHdrMgr"
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|
)
|
|
*11 (BoundsColHdr
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|
tm "BoundsColHdrMgr"
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|
)
|
|
*12 (InitColHdr
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|
tm "InitColHdrMgr"
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|
)
|
|
*13 (EolColHdr
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|
tm "EolColHdrMgr"
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|
)
|
|
*14 (LogPort
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port (LogicalPort
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|
decl (Decl
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|
n "clock"
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t "std_ulogic"
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o 1
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suid 9,0
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)
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)
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|
uid 237,0
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)
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|
*15 (LogPort
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|
port (LogicalPort
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|
decl (Decl
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|
n "memDataIn"
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t "std_ulogic_vector"
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|
b "(dataBitNb-1 DOWNTO 0)"
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o 2
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suid 10,0
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)
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)
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|
uid 239,0
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|
)
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*16 (LogPort
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|
port (LogicalPort
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|
m 1
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|
decl (Decl
|
|
n "ramDataIn"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
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o 13
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suid 11,0
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)
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)
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|
uid 241,0
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)
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*17 (LogPort
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port (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
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o 8
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suid 12,0
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)
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)
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|
uid 243,0
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)
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*18 (LogPort
|
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port (LogicalPort
|
|
decl (Decl
|
|
n "sampleData"
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|
t "std_ulogic"
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|
o 34
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suid 13,0
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)
|
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)
|
|
uid 245,0
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)
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]
|
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)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 94,0
|
|
optionalChildren [
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|
*19 (Sheet
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|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
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font "courier,10,0"
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|
)
|
|
emptyMRCItem *20 (MRCItem
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litem &1
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pos 5
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dimension 20
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)
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uid 96,0
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optionalChildren [
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*21 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 97,0
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)
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*22 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 98,0
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)
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*23 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 99,0
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)
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*24 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 238,0
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)
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*25 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 240,0
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)
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*26 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 242,0
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)
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*27 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 244,0
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)
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*28 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 246,0
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)
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]
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)
|
|
sheetCol (SheetCol
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|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
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font "courier,10,0"
|
|
textAngle 90
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)
|
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uid 100,0
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|
optionalChildren [
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|
*29 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 101,0
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)
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*30 (MRCItem
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litem &7
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pos 1
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dimension 50
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|
uid 102,0
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|
)
|
|
*31 (MRCItem
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|
litem &8
|
|
pos 2
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dimension 100
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|
uid 103,0
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)
|
|
*32 (MRCItem
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litem &9
|
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pos 3
|
|
dimension 50
|
|
uid 104,0
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)
|
|
*33 (MRCItem
|
|
litem &10
|
|
pos 4
|
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dimension 100
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|
uid 105,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
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|
uid 106,0
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|
)
|
|
*35 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
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|
uid 107,0
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|
)
|
|
*36 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
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|
uid 108,0
|
|
)
|
|
]
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|
)
|
|
fixedCol 4
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|
fixedRow 2
|
|
name "Ports"
|
|
uid 95,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 80,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *37 (LEmptyRow
|
|
)
|
|
uid 110,0
|
|
optionalChildren [
|
|
*38 (RefLabelRowHdr
|
|
)
|
|
*39 (TitleRowHdr
|
|
)
|
|
*40 (FilterRowHdr
|
|
)
|
|
*41 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*42 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*43 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*44 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*45 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*46 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*47 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*48 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*49 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 159,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 122,0
|
|
optionalChildren [
|
|
*50 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *51 (MRCItem
|
|
litem &37
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 124,0
|
|
optionalChildren [
|
|
*52 (MRCItem
|
|
litem &38
|
|
pos 0
|
|
dimension 20
|
|
uid 125,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &39
|
|
pos 1
|
|
dimension 23
|
|
uid 126,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &40
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 127,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &49
|
|
pos 0
|
|
dimension 20
|
|
uid 160,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 128,0
|
|
optionalChildren [
|
|
*56 (MRCItem
|
|
litem &41
|
|
pos 0
|
|
dimension 20
|
|
uid 129,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &43
|
|
pos 1
|
|
dimension 50
|
|
uid 130,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
dimension 100
|
|
uid 131,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &45
|
|
pos 3
|
|
dimension 100
|
|
uid 132,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &46
|
|
pos 4
|
|
dimension 50
|
|
uid 133,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &47
|
|
pos 5
|
|
dimension 50
|
|
uid 134,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &48
|
|
pos 6
|
|
dimension 80
|
|
uid 135,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 123,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 109,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@sample@data@in/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@sample@data@in/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@sample@data@in"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerSampleDataIn"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "sdramControllerSampleDataIn"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:45:13"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Memory"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Libs/Memory/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "sdramControllerSampleDataIn"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Aug"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "August"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@sample@data@in/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerSampleDataIn/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\Board\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\EDA\\Modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:45:13"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
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variable "version"
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value "2018.1 (Build 12)"
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variable "view"
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value "symbol"
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variable "year"
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variable "yy"
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value "19"
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tm "CptPortNameMgr"
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tm "CptPortNameMgr"
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tm "CptPortNameMgr"
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