3272 lines
40 KiB
Plaintext
3272 lines
40 KiB
Plaintext
DocumentHdrVersion "1.1"
|
|
Header (DocumentHdr
|
|
version 2
|
|
dialect 11
|
|
dmPackageRefs [
|
|
(DmPackageRef
|
|
library "ieee"
|
|
unitName "std_logic_1164"
|
|
)
|
|
(DmPackageRef
|
|
library "ieee"
|
|
unitName "numeric_std"
|
|
itemName "ALL"
|
|
)
|
|
]
|
|
instances [
|
|
(Instance
|
|
name "I_tester"
|
|
duLibraryName "DigitalToAnalogConverter_test"
|
|
duName "DAC_tester"
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
(GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value "clockFrequency"
|
|
)
|
|
]
|
|
mwi 0
|
|
uid 421,0
|
|
)
|
|
(Instance
|
|
name "I_filt"
|
|
duLibraryName "WaveformGenerator"
|
|
duName "lowpass"
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
(GiElement
|
|
name "shiftBitNb"
|
|
type "positive"
|
|
value "lowpassShiftBitNb"
|
|
)
|
|
]
|
|
mwi 0
|
|
uid 1056,0
|
|
)
|
|
(Instance
|
|
name "I_DUT"
|
|
duLibraryName "DigitalToAnalogConverter"
|
|
duName "DAC"
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
]
|
|
mwi 0
|
|
uid 1298,0
|
|
)
|
|
]
|
|
embeddedInstances [
|
|
(EmbeddedInstance
|
|
name "eb1"
|
|
number "1"
|
|
)
|
|
]
|
|
libraryRefs [
|
|
"ieee"
|
|
]
|
|
)
|
|
version "32.1"
|
|
appVersion "2019.2 (Build 5)"
|
|
noEmbeddedEditors 1
|
|
model (BlockDiag
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\@d@a@c_tb\\struct.bd.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\@d@a@c_tb\\struct.bd.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\@d@a@c_tb"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\DAC_tb"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "DAC_tb"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:43:18"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "DigitalToAnalogConverter_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/DigitalToAnalogConverter_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "DAC_tb"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\@d@a@c_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\..\\DigitalToAnalogConverter_test\\hds\\DAC_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:43:18"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "DAC_tb"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 153,0
|
|
optionalChildren [
|
|
*1 (Net
|
|
uid 45,0
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 1,0
|
|
)
|
|
declText (MLText
|
|
uid 46,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,17000,15200,18000"
|
|
st "SIGNAL reset : std_ulogic"
|
|
)
|
|
)
|
|
*2 (Net
|
|
uid 53,0
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 2,0
|
|
)
|
|
declText (MLText
|
|
uid 54,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,13000,15200,14000"
|
|
st "SIGNAL clock : std_ulogic"
|
|
)
|
|
)
|
|
*3 (Grouping
|
|
uid 110,0
|
|
optionalChildren [
|
|
*4 (CommentText
|
|
uid 112,0
|
|
shape (Rectangle
|
|
uid 113,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "44000,54000,61000,55000"
|
|
)
|
|
oxt "18000,70000,35000,71000"
|
|
text (MLText
|
|
uid 114,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "44200,54500,44200,54500"
|
|
st "
|
|
by %user on %dd %month %year
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*5 (CommentText
|
|
uid 115,0
|
|
shape (Rectangle
|
|
uid 116,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "61000,50000,65000,51000"
|
|
)
|
|
oxt "35000,66000,39000,67000"
|
|
text (MLText
|
|
uid 117,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "61200,50500,61200,50500"
|
|
st "
|
|
Project:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*6 (CommentText
|
|
uid 118,0
|
|
shape (Rectangle
|
|
uid 119,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "44000,52000,61000,53000"
|
|
)
|
|
oxt "18000,68000,35000,69000"
|
|
text (MLText
|
|
uid 120,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "44200,52500,44200,52500"
|
|
st "
|
|
<enter diagram title here>
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*7 (CommentText
|
|
uid 121,0
|
|
shape (Rectangle
|
|
uid 122,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "40000,52000,44000,53000"
|
|
)
|
|
oxt "14000,68000,18000,69000"
|
|
text (MLText
|
|
uid 123,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "40200,52500,40200,52500"
|
|
st "
|
|
Title:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*8 (CommentText
|
|
uid 124,0
|
|
shape (Rectangle
|
|
uid 125,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "61000,51000,81000,55000"
|
|
)
|
|
oxt "35000,67000,55000,71000"
|
|
text (MLText
|
|
uid 126,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "61200,51200,75300,52400"
|
|
st "
|
|
<enter comments here>
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 4000
|
|
visibleWidth 20000
|
|
)
|
|
ignorePrefs 1
|
|
)
|
|
*9 (CommentText
|
|
uid 127,0
|
|
shape (Rectangle
|
|
uid 128,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "65000,50000,81000,51000"
|
|
)
|
|
oxt "39000,66000,55000,67000"
|
|
text (MLText
|
|
uid 129,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "65200,50500,65200,50500"
|
|
st "
|
|
<enter project name here>
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 16000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*10 (CommentText
|
|
uid 130,0
|
|
shape (Rectangle
|
|
uid 131,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "40000,50000,61000,52000"
|
|
)
|
|
oxt "14000,66000,35000,68000"
|
|
text (MLText
|
|
uid 132,0
|
|
va (VaSet
|
|
fg "32768,0,0"
|
|
)
|
|
xt "45350,50400,55650,51600"
|
|
st "
|
|
<company name>
|
|
"
|
|
ju 0
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 2000
|
|
visibleWidth 21000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*11 (CommentText
|
|
uid 133,0
|
|
shape (Rectangle
|
|
uid 134,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "40000,53000,44000,54000"
|
|
)
|
|
oxt "14000,69000,18000,70000"
|
|
text (MLText
|
|
uid 135,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "40200,53500,40200,53500"
|
|
st "
|
|
Path:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*12 (CommentText
|
|
uid 136,0
|
|
shape (Rectangle
|
|
uid 137,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "40000,54000,44000,55000"
|
|
)
|
|
oxt "14000,70000,18000,71000"
|
|
text (MLText
|
|
uid 138,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "40200,54500,40200,54500"
|
|
st "
|
|
Edited:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*13 (CommentText
|
|
uid 139,0
|
|
shape (Rectangle
|
|
uid 140,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "44000,53000,61000,54000"
|
|
)
|
|
oxt "18000,69000,35000,70000"
|
|
text (MLText
|
|
uid 141,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "44200,53500,44200,53500"
|
|
st "
|
|
%library/%unit/%view
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
]
|
|
shape (GroupingShape
|
|
uid 111,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
lineWidth 2
|
|
)
|
|
xt "40000,50000,81000,55000"
|
|
)
|
|
oxt "14000,66000,55000,71000"
|
|
)
|
|
*14 (Net
|
|
uid 362,0
|
|
decl (Decl
|
|
n "parallelIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 3,0
|
|
)
|
|
declText (MLText
|
|
uid 363,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,16000,26400,17000"
|
|
st "SIGNAL parallelIn : unsigned(signalBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*15 (Net
|
|
uid 364,0
|
|
decl (Decl
|
|
n "serialOut"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 4,0
|
|
)
|
|
declText (MLText
|
|
uid 365,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,18000,15500,19000"
|
|
st "SIGNAL serialOut : std_ulogic"
|
|
)
|
|
)
|
|
*16 (Blk
|
|
uid 421,0
|
|
shape (Rectangle
|
|
uid 422,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "40000,56832,65535"
|
|
)
|
|
xt "1000,40000,79000,48000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
|
ttg (MlTextGroup
|
|
uid 423,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*17 (Text
|
|
uid 424,0
|
|
va (VaSet
|
|
)
|
|
xt "1700,48200,19500,49400"
|
|
st "DigitalToAnalogConverter_test"
|
|
blo "1700,49200"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*18 (Text
|
|
uid 425,0
|
|
va (VaSet
|
|
)
|
|
xt "1700,49400,9100,50600"
|
|
st "DAC_tester"
|
|
blo "1700,50400"
|
|
tm "BlkNameMgr"
|
|
)
|
|
*19 (Text
|
|
uid 426,0
|
|
va (VaSet
|
|
)
|
|
xt "1700,50600,6500,51800"
|
|
st "I_tester"
|
|
blo "1700,51600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 427,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 428,0
|
|
text (MLText
|
|
uid 429,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,52000,28200,54400"
|
|
st "signalBitNb = signalBitNb ( positive )
|
|
clockFrequency = clockFrequency ( real )
|
|
"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
(GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value "clockFrequency"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
*20 (SaComponent
|
|
uid 1056,0
|
|
optionalChildren [
|
|
*21 (CptPort
|
|
uid 1040,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1041,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50250,27625,51000,28375"
|
|
)
|
|
tg (CPTG
|
|
uid 1042,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1043,0
|
|
va (VaSet
|
|
)
|
|
xt "52000,27400,55400,28600"
|
|
st "clock"
|
|
blo "52000,28400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*22 (CptPort
|
|
uid 1044,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1045,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "67000,23625,67750,24375"
|
|
)
|
|
tg (CPTG
|
|
uid 1046,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1047,0
|
|
va (VaSet
|
|
)
|
|
xt "58700,23400,66000,24600"
|
|
st "lowpassOut"
|
|
ju 2
|
|
blo "66000,24400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "lowpassOut"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*23 (CptPort
|
|
uid 1048,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1049,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50250,29625,51000,30375"
|
|
)
|
|
tg (CPTG
|
|
uid 1050,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1051,0
|
|
va (VaSet
|
|
)
|
|
xt "52000,29400,55300,30600"
|
|
st "reset"
|
|
blo "52000,30400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*24 (CptPort
|
|
uid 1052,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1053,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50250,23625,51000,24375"
|
|
)
|
|
tg (CPTG
|
|
uid 1054,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1055,0
|
|
va (VaSet
|
|
)
|
|
xt "52000,23400,57800,24600"
|
|
st "lowpassIn"
|
|
blo "52000,24400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "lowpassIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1057,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "51000,20000,67000,32000"
|
|
)
|
|
oxt "32000,10000,48000,22000"
|
|
ttg (MlTextGroup
|
|
uid 1058,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*25 (Text
|
|
uid 1059,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "51600,31800,63100,33000"
|
|
st "WaveformGenerator"
|
|
blo "51600,32800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*26 (Text
|
|
uid 1060,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "51600,33000,56200,34200"
|
|
st "lowpass"
|
|
blo "51600,34000"
|
|
tm "CptNameMgr"
|
|
)
|
|
*27 (Text
|
|
uid 1061,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "51600,34200,54900,35400"
|
|
st "I_filt"
|
|
blo "51600,35200"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1062,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1063,0
|
|
text (MLText
|
|
uid 1064,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "51000,35600,71800,37600"
|
|
st "signalBitNb = signalBitNb ( positive )
|
|
shiftBitNb = lowpassShiftBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
(GiElement
|
|
name "shiftBitNb"
|
|
type "positive"
|
|
value "lowpassShiftBitNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*28 (Net
|
|
uid 1081,0
|
|
decl (Decl
|
|
n "lowpassOut"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 3
|
|
suid 8,0
|
|
)
|
|
declText (MLText
|
|
uid 1082,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,15000,27300,16000"
|
|
st "SIGNAL lowpassOut : unsigned(signalBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*29 (Net
|
|
uid 1091,0
|
|
decl (Decl
|
|
n "lowpassIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 2
|
|
suid 9,0
|
|
)
|
|
declText (MLText
|
|
uid 1092,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,14000,27000,15000"
|
|
st "SIGNAL lowpassIn : unsigned(signalBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*30 (HdlText
|
|
uid 1099,0
|
|
optionalChildren [
|
|
*31 (EmbeddedText
|
|
uid 1104,0
|
|
commentText (CommentText
|
|
uid 1105,0
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
uid 1106,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "35000,13000,51000,15000"
|
|
)
|
|
oxt "0,0,18000,5000"
|
|
text (MLText
|
|
uid 1107,0
|
|
va (VaSet
|
|
)
|
|
xt "35200,13200,50300,14400"
|
|
st "
|
|
LowpassIn <= (others => serialOut);
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 2000
|
|
visibleWidth 16000
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1100,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "35000,12000,51000,16000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
|
ttg (MlTextGroup
|
|
uid 1101,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*32 (Text
|
|
uid 1102,0
|
|
va (VaSet
|
|
)
|
|
xt "35400,16000,38000,17200"
|
|
st "eb1"
|
|
blo "35400,17000"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*33 (Text
|
|
uid 1103,0
|
|
va (VaSet
|
|
)
|
|
xt "35400,17000,36800,18200"
|
|
st "1"
|
|
blo "35400,18000"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
*34 (SaComponent
|
|
uid 1298,0
|
|
optionalChildren [
|
|
*35 (CptPort
|
|
uid 1282,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1283,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "18250,27625,19000,28375"
|
|
)
|
|
tg (CPTG
|
|
uid 1284,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1285,0
|
|
va (VaSet
|
|
)
|
|
xt "20000,27400,23400,28600"
|
|
st "clock"
|
|
blo "20000,28400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*36 (CptPort
|
|
uid 1286,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1287,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "18250,23625,19000,24375"
|
|
)
|
|
tg (CPTG
|
|
uid 1288,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1289,0
|
|
va (VaSet
|
|
)
|
|
xt "20000,23400,26200,24600"
|
|
st "parallelIn"
|
|
blo "20000,24400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "parallelIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*37 (CptPort
|
|
uid 1290,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1291,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "35000,23625,35750,24375"
|
|
)
|
|
tg (CPTG
|
|
uid 1292,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1293,0
|
|
va (VaSet
|
|
)
|
|
xt "28601,23400,34001,24600"
|
|
st "serialOut"
|
|
ju 2
|
|
blo "34001,24400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "serialOut"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*38 (CptPort
|
|
uid 1294,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1295,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "18250,29625,19000,30375"
|
|
)
|
|
tg (CPTG
|
|
uid 1296,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1297,0
|
|
va (VaSet
|
|
)
|
|
xt "20000,29400,23300,30600"
|
|
st "reset"
|
|
blo "20000,30400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1299,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "19000,20000,35000,32000"
|
|
)
|
|
oxt "32000,14000,48000,26000"
|
|
ttg (MlTextGroup
|
|
uid 1300,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*39 (Text
|
|
uid 1301,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "19600,31800,34300,33000"
|
|
st "DigitalToAnalogConverter"
|
|
blo "19600,32800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*40 (Text
|
|
uid 1302,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "19600,32700,22300,33900"
|
|
st "DAC"
|
|
blo "19600,33700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*41 (Text
|
|
uid 1303,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "19600,33600,23300,34800"
|
|
st "I_DUT"
|
|
blo "19600,34600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1304,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1305,0
|
|
text (MLText
|
|
uid 1306,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "19000,35600,37400,36600"
|
|
st "signalBitNb = signalBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
connectByName 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*42 (Wire
|
|
uid 47,0
|
|
shape (OrthoPolyLine
|
|
uid 48,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "15000,30000,18250,40000"
|
|
pts [
|
|
"15000,40000"
|
|
"15000,30000"
|
|
"18250,30000"
|
|
]
|
|
)
|
|
start &16
|
|
end &38
|
|
sat 2
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 51,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 52,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "15000,28600,19100,30000"
|
|
st "reset"
|
|
blo "15000,29800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &1
|
|
)
|
|
*43 (Wire
|
|
uid 55,0
|
|
shape (OrthoPolyLine
|
|
uid 56,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "13000,28000,18250,40000"
|
|
pts [
|
|
"13000,40000"
|
|
"13000,28000"
|
|
"18250,28000"
|
|
]
|
|
)
|
|
start &16
|
|
end &35
|
|
sat 2
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 59,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 60,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "15000,26600,18800,28000"
|
|
st "clock"
|
|
blo "15000,27800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*44 (Wire
|
|
uid 63,0
|
|
shape (OrthoPolyLine
|
|
uid 64,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "9000,24000,18250,40000"
|
|
pts [
|
|
"9000,40000"
|
|
"9000,24000"
|
|
"18250,24000"
|
|
]
|
|
)
|
|
start &16
|
|
end &36
|
|
sat 2
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 67,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 68,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "9000,22600,16500,24000"
|
|
st "parallelIn"
|
|
blo "9000,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &14
|
|
)
|
|
*45 (Wire
|
|
uid 366,0
|
|
optionalChildren [
|
|
*46 (BdJunction
|
|
uid 1114,0
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
uid 1115,0
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "38600,23600,39400,24400"
|
|
radius 400
|
|
)
|
|
)
|
|
]
|
|
shape (OrthoPolyLine
|
|
uid 367,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "35750,24000,43000,40000"
|
|
pts [
|
|
"35750,24000"
|
|
"43000,24000"
|
|
"43000,40000"
|
|
]
|
|
)
|
|
start &37
|
|
end &16
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 370,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 371,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "37000,22600,43500,24000"
|
|
st "serialOut"
|
|
blo "37000,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &15
|
|
)
|
|
*47 (Wire
|
|
uid 1065,0
|
|
shape (OrthoPolyLine
|
|
uid 1066,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "47000,30000,50250,30000"
|
|
pts [
|
|
"47000,30000"
|
|
"50250,30000"
|
|
]
|
|
)
|
|
end &23
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1071,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1072,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "47000,28600,51100,30000"
|
|
st "reset"
|
|
blo "47000,29800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &1
|
|
)
|
|
*48 (Wire
|
|
uid 1073,0
|
|
shape (OrthoPolyLine
|
|
uid 1074,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "47000,28000,50250,28000"
|
|
pts [
|
|
"47000,28000"
|
|
"50250,28000"
|
|
]
|
|
)
|
|
end &21
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1079,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1080,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "47000,26600,50800,28000"
|
|
st "clock"
|
|
blo "47000,27800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*49 (Wire
|
|
uid 1083,0
|
|
shape (OrthoPolyLine
|
|
uid 1084,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "67750,24000,71000,40000"
|
|
pts [
|
|
"67750,24000"
|
|
"71000,24000"
|
|
"71000,40000"
|
|
]
|
|
)
|
|
start &22
|
|
end &16
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1087,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1088,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "69750,22600,78850,24000"
|
|
st "lowpassOut"
|
|
blo "69750,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &28
|
|
)
|
|
*50 (Wire
|
|
uid 1093,0
|
|
shape (OrthoPolyLine
|
|
uid 1094,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "47000,16000,50250,24000"
|
|
pts [
|
|
"50250,24000"
|
|
"47000,24000"
|
|
"47000,16000"
|
|
]
|
|
)
|
|
start &24
|
|
end &30
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1097,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1098,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "44000,22600,51300,24000"
|
|
st "lowpassIn"
|
|
blo "44000,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &29
|
|
)
|
|
*51 (Wire
|
|
uid 1108,0
|
|
shape (OrthoPolyLine
|
|
uid 1109,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "39000,16000,39000,24000"
|
|
pts [
|
|
"39000,24000"
|
|
"39000,16000"
|
|
]
|
|
)
|
|
start &46
|
|
end &30
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1112,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1113,0
|
|
ro 270
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "37600,18000,39000,24500"
|
|
st "serialOut"
|
|
blo "38800,24500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &15
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 0
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *52 (PackageList
|
|
uid 142,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*53 (Text
|
|
uid 143,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,0,6900,1000"
|
|
st "Package List"
|
|
blo "0,800"
|
|
)
|
|
*54 (MLText
|
|
uid 144,0
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,17500,4600"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.ALL;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 145,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*55 (Text
|
|
uid 146,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,0,30200,1000"
|
|
st "Compiler Directives"
|
|
blo "20000,800"
|
|
)
|
|
*56 (Text
|
|
uid 147,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,1000,32200,2000"
|
|
st "Pre-module directives:"
|
|
blo "20000,1800"
|
|
)
|
|
*57 (MLText
|
|
uid 148,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,2000,32100,4400"
|
|
st "`resetall
|
|
`timescale 1ns/10ps"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*58 (Text
|
|
uid 149,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,4000,32800,5000"
|
|
st "Post-module directives:"
|
|
blo "20000,4800"
|
|
)
|
|
*59 (MLText
|
|
uid 150,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,0,20000,0"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*60 (Text
|
|
uid 151,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,5000,32400,6000"
|
|
st "End-module directives:"
|
|
blo "20000,5800"
|
|
)
|
|
*61 (MLText
|
|
uid 152,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,6000,20000,6000"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
]
|
|
associable 1
|
|
)
|
|
windowSize "-8,-8,1928,1048"
|
|
viewArea "-1193,-1193,104962,56484"
|
|
cachedDiagramExtent "0,0,81000,55000"
|
|
pageSetupInfo (PageSetupInfo
|
|
ptrCmd "Generic PostScript Printer,winspool,"
|
|
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
|
|
toPrinter 1
|
|
xMargin 48
|
|
yMargin 48
|
|
paperWidth 1077
|
|
paperHeight 761
|
|
unixPaperWidth 595
|
|
unixPaperHeight 842
|
|
windowsPaperWidth 1077
|
|
windowsPaperHeight 761
|
|
paperType "A4"
|
|
unixPaperName "A4 (210mm x 297mm)"
|
|
windowsPaperName "A4"
|
|
scale 90
|
|
exportedDirectories [
|
|
"$HDS_PROJECT_DIR/HTMLExport"
|
|
]
|
|
boundaryWidth 0
|
|
)
|
|
hasePageBreakOrigin 1
|
|
pageBreakOrigin "0,0"
|
|
lastUid 1552,0
|
|
defaultCommentText (CommentText
|
|
shape (Rectangle
|
|
layer 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,15000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
fg "65535,0,0"
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 14600
|
|
)
|
|
)
|
|
defaultRequirementText (RequirementText
|
|
shape (ZoomableIcon
|
|
layer 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "59904,39936,65280"
|
|
lineColor "0,0,32768"
|
|
)
|
|
xt "0,0,1500,1750"
|
|
iconName "reqTracerRequirement.bmp"
|
|
iconMaskName "reqTracerRequirement.msk"
|
|
)
|
|
autoResize 1
|
|
text (MLText
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "450,2150,1450,3150"
|
|
st "
|
|
Text
|
|
"
|
|
tm "RequirementText"
|
|
wrapOption 3
|
|
visibleHeight 1350
|
|
visibleWidth 1100
|
|
)
|
|
)
|
|
defaultPanel (Panel
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "32768,0,0"
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (Text
|
|
va (VaSet
|
|
font "Verdana,10,1"
|
|
)
|
|
xt "1000,1000,4400,2200"
|
|
st "Panel0"
|
|
blo "1000,2000"
|
|
tm "PanelText"
|
|
)
|
|
)
|
|
)
|
|
defaultBlk (Blk
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "40000,56832,65535"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*62 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,3200,6300,4400"
|
|
st "<library>"
|
|
blo "1700,4200"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*63 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,4400,5800,5600"
|
|
st "<block>"
|
|
blo "1700,5400"
|
|
tm "BlkNameMgr"
|
|
)
|
|
*64 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,5600,2900,6800"
|
|
st "I0"
|
|
blo "1700,6600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "1700,13200,1700,13200"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
)
|
|
defaultMWComponent (MWC
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*65 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,3500,3300,4500"
|
|
st "Library"
|
|
blo "1000,4300"
|
|
)
|
|
*66 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,4500,7000,5500"
|
|
st "MWComponent"
|
|
blo "1000,5300"
|
|
)
|
|
*67 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,5500,1600,6500"
|
|
st "I0"
|
|
blo "1000,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6000,1500,-6000,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
prms (Property
|
|
pclass "params"
|
|
pname "params"
|
|
ptn "String"
|
|
)
|
|
visOptions (mwParamsVisibilityOptions
|
|
)
|
|
)
|
|
defaultSaComponent (SaComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*68 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,3500,3550,4500"
|
|
st "Library"
|
|
blo "1250,4300"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*69 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,4500,6750,5500"
|
|
st "SaComponent"
|
|
blo "1250,5300"
|
|
tm "CptNameMgr"
|
|
)
|
|
*70 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,5500,1850,6500"
|
|
st "I0"
|
|
blo "1250,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-5750,1500,-5750,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
defaultVhdlComponent (VhdlComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*71 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,3500,3250,4500"
|
|
st "Library"
|
|
blo "950,4300"
|
|
)
|
|
*72 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,4500,7050,5500"
|
|
st "VhdlComponent"
|
|
blo "950,5300"
|
|
)
|
|
*73 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,5500,1550,6500"
|
|
st "I0"
|
|
blo "950,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6050,1500,-6050,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
archName ""
|
|
archPath ""
|
|
)
|
|
defaultVerilogComponent (VerilogComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "-50,0,8050,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*74 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,3500,2750,4500"
|
|
st "Library"
|
|
blo "450,4300"
|
|
)
|
|
*75 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,4500,7550,5500"
|
|
st "VerilogComponent"
|
|
blo "450,5300"
|
|
)
|
|
*76 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,5500,1050,6500"
|
|
st "I0"
|
|
blo "450,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6550,1500,-6550,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*77 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,4000,4600,5000"
|
|
st "eb1"
|
|
blo "3400,4800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*78 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,5000,3800,6000"
|
|
st "1"
|
|
blo "3400,5800"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
)
|
|
xt "-300,-500,300,500"
|
|
st "G"
|
|
blo "-300,300"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*79 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*80 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*81 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*82 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5000,7000,6000"
|
|
st "Declarations"
|
|
blo "0,5800"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6000,3400,7000"
|
|
st "Ports:"
|
|
blo "0,6800"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7000,4800,8000"
|
|
st "Pre User:"
|
|
blo "0,7800"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,8000,21800,12000"
|
|
st "constant signalBitNb: positive := 16;
|
|
constant lowpassShiftBitNb: positive := 8;
|
|
constant clockFrequency: real := 60.0E6;
|
|
--constant clockFrequency: real := 66.0E6;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,12000,9000,13000"
|
|
st "Diagram Signals:"
|
|
blo "0,12800"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5000,6000,6000"
|
|
st "Post User:"
|
|
blo "0,5800"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,5000,0,5000"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 9,0
|
|
usingSuid 1
|
|
emptyRow *83 (LEmptyRow
|
|
)
|
|
uid 727,0
|
|
optionalChildren [
|
|
*84 (RefLabelRowHdr
|
|
)
|
|
*85 (TitleRowHdr
|
|
)
|
|
*86 (FilterRowHdr
|
|
)
|
|
*87 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*88 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*89 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*90 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*91 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*92 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*93 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*94 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*95 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*96 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 714,0
|
|
)
|
|
*97 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 716,0
|
|
)
|
|
*98 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "parallelIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 718,0
|
|
)
|
|
*99 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "serialOut"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 4,0
|
|
)
|
|
)
|
|
uid 720,0
|
|
)
|
|
*100 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "lowpassOut"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 3
|
|
suid 8,0
|
|
)
|
|
)
|
|
uid 1089,0
|
|
)
|
|
*101 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "lowpassIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 2
|
|
suid 9,0
|
|
)
|
|
)
|
|
uid 1116,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 740,0
|
|
optionalChildren [
|
|
*102 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *103 (MRCItem
|
|
litem &83
|
|
pos 6
|
|
dimension 20
|
|
)
|
|
uid 742,0
|
|
optionalChildren [
|
|
*104 (MRCItem
|
|
litem &84
|
|
pos 0
|
|
dimension 20
|
|
uid 743,0
|
|
)
|
|
*105 (MRCItem
|
|
litem &85
|
|
pos 1
|
|
dimension 23
|
|
uid 744,0
|
|
)
|
|
*106 (MRCItem
|
|
litem &86
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 745,0
|
|
)
|
|
*107 (MRCItem
|
|
litem &96
|
|
pos 0
|
|
dimension 20
|
|
uid 715,0
|
|
)
|
|
*108 (MRCItem
|
|
litem &97
|
|
pos 1
|
|
dimension 20
|
|
uid 717,0
|
|
)
|
|
*109 (MRCItem
|
|
litem &98
|
|
pos 2
|
|
dimension 20
|
|
uid 719,0
|
|
)
|
|
*110 (MRCItem
|
|
litem &99
|
|
pos 3
|
|
dimension 20
|
|
uid 721,0
|
|
)
|
|
*111 (MRCItem
|
|
litem &100
|
|
pos 4
|
|
dimension 20
|
|
uid 1090,0
|
|
)
|
|
*112 (MRCItem
|
|
litem &101
|
|
pos 5
|
|
dimension 20
|
|
uid 1117,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 746,0
|
|
optionalChildren [
|
|
*113 (MRCItem
|
|
litem &87
|
|
pos 0
|
|
dimension 20
|
|
uid 747,0
|
|
)
|
|
*114 (MRCItem
|
|
litem &89
|
|
pos 1
|
|
dimension 50
|
|
uid 748,0
|
|
)
|
|
*115 (MRCItem
|
|
litem &90
|
|
pos 2
|
|
dimension 100
|
|
uid 749,0
|
|
)
|
|
*116 (MRCItem
|
|
litem &91
|
|
pos 3
|
|
dimension 50
|
|
uid 750,0
|
|
)
|
|
*117 (MRCItem
|
|
litem &92
|
|
pos 4
|
|
dimension 100
|
|
uid 751,0
|
|
)
|
|
*118 (MRCItem
|
|
litem &93
|
|
pos 5
|
|
dimension 100
|
|
uid 752,0
|
|
)
|
|
*119 (MRCItem
|
|
litem &94
|
|
pos 6
|
|
dimension 50
|
|
uid 753,0
|
|
)
|
|
*120 (MRCItem
|
|
litem &95
|
|
pos 7
|
|
dimension 80
|
|
uid 754,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 741,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 726,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *121 (LEmptyRow
|
|
)
|
|
uid 756,0
|
|
optionalChildren [
|
|
*122 (RefLabelRowHdr
|
|
)
|
|
*123 (TitleRowHdr
|
|
)
|
|
*124 (FilterRowHdr
|
|
)
|
|
*125 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*126 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*127 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*128 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*129 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*130 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*131 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*132 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 768,0
|
|
optionalChildren [
|
|
*133 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *134 (MRCItem
|
|
litem &121
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 770,0
|
|
optionalChildren [
|
|
*135 (MRCItem
|
|
litem &122
|
|
pos 0
|
|
dimension 20
|
|
uid 771,0
|
|
)
|
|
*136 (MRCItem
|
|
litem &123
|
|
pos 1
|
|
dimension 23
|
|
uid 772,0
|
|
)
|
|
*137 (MRCItem
|
|
litem &124
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 773,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 774,0
|
|
optionalChildren [
|
|
*138 (MRCItem
|
|
litem &125
|
|
pos 0
|
|
dimension 20
|
|
uid 775,0
|
|
)
|
|
*139 (MRCItem
|
|
litem &127
|
|
pos 1
|
|
dimension 50
|
|
uid 776,0
|
|
)
|
|
*140 (MRCItem
|
|
litem &128
|
|
pos 2
|
|
dimension 100
|
|
uid 777,0
|
|
)
|
|
*141 (MRCItem
|
|
litem &129
|
|
pos 3
|
|
dimension 100
|
|
uid 778,0
|
|
)
|
|
*142 (MRCItem
|
|
litem &130
|
|
pos 4
|
|
dimension 50
|
|
uid 779,0
|
|
)
|
|
*143 (MRCItem
|
|
litem &131
|
|
pos 5
|
|
dimension 50
|
|
uid 780,0
|
|
)
|
|
*144 (MRCItem
|
|
litem &132
|
|
pos 6
|
|
dimension 80
|
|
uid 781,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 769,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 755,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|