84 lines
2.4 KiB
VHDL
84 lines
2.4 KiB
VHDL
ARCHITECTURE test OF bram_tester IS
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constant clockFrequencyA: real := 66.0E6;
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constant clockFrequencyB: real := 20.0E6;
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constant clockPeriodA: time := (1.0/clockFrequencyA) * 1 sec;
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constant clockPeriodB: time := (1.0/clockFrequencyB) * 1 sec;
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signal clockA_int: std_uLogic := '1';
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signal clockB_int: std_uLogic := '1';
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signal addressA_int: natural;
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signal dataA_int: integer;
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signal addressB_int: natural;
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signal dataB_int: integer;
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BEGIN
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------------------------------------------------------------------------------
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-- clocks
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clockA_int <= not clockA_int after clockPeriodA/2;
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clockA <= transport clockA_int after clockPeriodA*9/10;
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clockB_int <= not clockB_int after clockPeriodB/2;
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clockB <= transport clockB_int after clockPeriodB*9/10;
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------------------------------------------------------------------------------
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-- test sequence
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portA: process
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begin
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enA <= '0';
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writeEnA <= '0';
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addressA_int <= 0;
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dataA_int <= 0;
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-- read initial BRAM data
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wait for 5*clockPeriodA;
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addressA_int <= 40;
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enA <= '1';
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wait for clockPeriodA;
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enA <= '0';
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-- write data on port A
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wait for 10*clockPeriodA;
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addressA_int <= 10;
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dataA_int <= 5;
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enA <= '1';
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writeEnA <= '1';
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wait for clockPeriodA;
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enA <= '0';
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writeEnA <= '0';
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wait;
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end process portA;
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addressA <= std_ulogic_vector(to_unsigned(addressA_int, addressA'length));
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dataInA <= std_ulogic_vector(to_signed(dataA_int, dataInA'length));
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portB: process
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begin
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enB <= '0';
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writeEnB <= '0';
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addressB_int <= 0;
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dataB_int <= 0;
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-- write data on port B
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wait for 10*clockPeriodB;
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addressB_int <= 20;
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dataB_int <= 10;
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enB <= '1';
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writeEnB <= '1';
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wait for clockPeriodB;
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enB <= '0';
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writeEnB <= '0';
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-- read data written on port A
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wait for 2*clockPeriodB;
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addressB_int <= 10;
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enB <= '1';
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wait for clockPeriodB;
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enB <= '0';
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wait;
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end process portB;
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addressB <= std_ulogic_vector(to_unsigned(addressB_int, addressB'length));
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dataInB <= std_ulogic_vector(to_signed(dataB_int, dataInB'length));
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END ARCHITECTURE test;
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