42 lines
1.1 KiB
VHDL
42 lines
1.1 KiB
VHDL
USE std.textio.all;
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ARCHITECTURE bhv OF bramDualport IS
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-- Define ramContent type
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type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector(dataBitNb-1 DOWNTO 0);
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-- Declare ramContent signal
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shared variable ramContent: ramContentType;
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BEGIN
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-- Port A
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process(clockA)
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begin
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if clockA'event and clockA='1' then
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if enA = '1' then
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if writeEnA = '1' then
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dataOutA <= dataInA;
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ramContent(to_integer(unsigned(addressA))) := to_bitvector(dataInA,'0');
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else
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dataOutA <= to_stdulogicvector(ramContent(to_integer(unsigned(addressA))));
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end if;
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end if;
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end if;
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end process;
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-- Port B
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process(clockB)
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begin
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if clockB'event and clockB='1' then
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if enB = '1' then
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if writeEnB = '1' then
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ramContent(to_integer(unsigned(addressB))) := to_bitvector(dataInB,'0');
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dataOutB <= dataInB;
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else
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dataOutB <= to_stdulogicvector(ramContent(to_integer(unsigned(addressB))));
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end if;
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end if;
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end if;
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end process;
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END ARCHITECTURE bhv;
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