3026 lines
37 KiB
Plaintext
3026 lines
37 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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instances [
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(Instance
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name "I_tester"
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duLibraryName "pipelinedOperators_test"
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duName "pipelineAdder_tester"
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elements [
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(GiElement
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name "adderBitNb"
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type "positive"
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value "adderBitNb"
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(GiElement
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name "stageNb"
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name "clockFrequency"
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value "clockFrequency"
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mwi 0
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(Instance
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name "I_DUT"
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duLibraryName "pipelinedOperators"
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duName "pipelineAdder"
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elements [
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(GiElement
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name "bitNb"
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type "positive"
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value "adderBitNb"
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name "stageNb"
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value "pipelineStageNb"
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mwi 0
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libraryRefs [
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"ieee"
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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vvMap [
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(vvPair
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variable " "
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value " "
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl"
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(vvPair
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variable "HDSDir"
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tb\\struct.bd.info"
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tb\\struct.bd.user"
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(vvPair
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variable "SourceDir"
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variable "appl"
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value "HDL Designer"
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value "struct"
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value "beamer.asm"
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value "%(unit)_%(view)_config"
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variable "date"
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value "ven."
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value "vendredi"
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variable "dd"
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value "28"
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variable "designName"
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value "$DESIGN_NAME"
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value "pipelineAdder_tb"
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variable "ext"
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value "<TBD>"
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value "struct.bd"
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value "struct.bd"
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value "UNKNOWN"
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value "WE7860"
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value "15:20:22"
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variable "group"
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value "UNKNOWN"
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variable "host"
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value "WE7860"
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variable "language"
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value "VHDL"
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variable "library"
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value "PipelinedOperators_test"
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(vvPair
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variable "library_downstream_ModelSim"
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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(vvPair
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variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/PipelinedOperators_test"
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(vvPair
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variable "mm"
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value "04"
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(vvPair
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variable "module_name"
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value "pipelineAdder_tb"
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(vvPair
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variable "month"
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value "avr."
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variable "month_long"
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value "avril"
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variable "p"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tb\\struct.bd"
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(vvPair
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variable "p_logical"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineAdder_tb\\struct.bd"
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(vvPair
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variable "package_name"
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value "<Undefined Variable>"
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(vvPair
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variable "project_name"
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value "hds"
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(vvPair
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variable "series"
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value "HDL Designer Series"
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(vvPair
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variable "task_ADMS"
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value "<TBD>"
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(vvPair
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variable "task_AsmPath"
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value "$HEI_LIBS_DIR/NanoBlaze/hdl"
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(vvPair
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variable "task_DesignCompilerPath"
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value "<TBD>"
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(vvPair
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variable "task_HDSPath"
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value "$HDS_HOME"
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variable "task_ISEBinPath"
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(vvPair
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variable "task_ISEPath"
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value "$ISE_WORK_DIR"
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(vvPair
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variable "task_LeonardoPath"
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value "<TBD>"
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value "/usr/opt/Modelsim/modeltech/bin"
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variable "task_NC"
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value "<TBD>"
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(vvPair
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variable "task_PrecisionRTLPath"
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value "<TBD>"
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(vvPair
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value "<TBD>"
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value "<TBD>"
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value "struct"
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stg "VerticalLayoutStrategy"
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tm "BdLibraryNameMgr"
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tm "BlkNameMgr"
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uid 2240,0
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decl (Decl
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declText (MLText
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uid 2256,0
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decl (Decl
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n "b"
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t "signed"
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suid 22,0
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)
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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uid 2264,0
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decl (Decl
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b "(adderBitNb-1 DOWNTO 0)"
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|
suid 23,0
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)
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declText (MLText
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uid 2265,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,13200,23400,14200"
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st "SIGNAL a : signed(adderBitNb-1 DOWNTO 0)"
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uid 2284,0
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decl (Decl
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n "sum"
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t "signed"
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o 7
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suid 24,0
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)
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declText (MLText
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uid 2285,0
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va (VaSet
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font "Verdana,8,0"
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st "SIGNAL sum : signed(adderBitNb-1 DOWNTO 0)"
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uid 2359,0
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uid 2331,0
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ro 180
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 2333,0
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stg "VerticalLayoutStrategy"
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f (Text
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uid 2334,0
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va (VaSet
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st "sum"
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)
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thePort (LogicalPort
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m 1
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decl (Decl
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n "sum"
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|
t "signed"
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b "(bitNb-1 downto 0)"
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|
o 1
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suid 1,0
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)
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)
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)
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*25 (CptPort
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uid 2335,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 2336,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
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uid 2337,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 2338,0
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va (VaSet
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)
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st "clock"
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blo "35000,20100"
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)
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)
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thePort (LogicalPort
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decl (Decl
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n "clock"
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|
t "std_ulogic"
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|
o 2
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|
suid 2,0
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)
|
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)
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)
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*26 (CptPort
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|
uid 2339,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 2340,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "33917,20625,34667,21375"
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tg (CPTG
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uid 2341,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 2342,0
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va (VaSet
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)
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st "reset"
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blo "35667,21100"
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)
|
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)
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thePort (LogicalPort
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decl (Decl
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n "reset"
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t "std_ulogic"
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|
suid 3,0
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)
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)
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)
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*27 (CptPort
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uid 2343,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 2344,0
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ro 270
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|
va (VaSet
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vasetType 1
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|
fg "0,65535,0"
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)
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|
xt "43334,17625,44084,18375"
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)
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|
tg (CPTG
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|
uid 2345,0
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|
ps "CptPortTextPlaceStrategy"
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|
stg "RightVerticalLayoutStrategy"
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f (Text
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|
uid 2346,0
|
|
va (VaSet
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)
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|
st "cIn"
|
|
ju 2
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|
blo "42334,18100"
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)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "cIn"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*28 (CptPort
|
|
uid 2347,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
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uid 2348,0
|
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ro 270
|
|
va (VaSet
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|
vasetType 1
|
|
fg "0,65535,0"
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)
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|
xt "31917,17625,32667,18375"
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)
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tg (CPTG
|
|
uid 2349,0
|
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ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2350,0
|
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va (VaSet
|
|
)
|
|
xt "33667,17400,35667,18300"
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|
st "cOut"
|
|
blo "33667,18100"
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)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "cOut"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 2005,0
|
|
)
|
|
)
|
|
)
|
|
*29 (CptPort
|
|
uid 2351,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 2352,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "33625,13250,34375,14000"
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)
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tg (CPTG
|
|
uid 2353,0
|
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ps "CptPortTextPlaceStrategy"
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|
stg "RightVerticalLayoutStrategy"
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|
f (Text
|
|
uid 2354,0
|
|
va (VaSet
|
|
)
|
|
xt "33800,14000,34300,14900"
|
|
st "a"
|
|
ju 2
|
|
blo "34300,14700"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "a"
|
|
t "signed"
|
|
b "(bitNb-1 downto 0)"
|
|
o 6
|
|
suid 2006,0
|
|
)
|
|
)
|
|
)
|
|
*30 (CptPort
|
|
uid 2355,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 2356,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41625,13250,42375,14000"
|
|
)
|
|
tg (CPTG
|
|
uid 2357,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2358,0
|
|
va (VaSet
|
|
)
|
|
xt "41800,14000,42300,14900"
|
|
st "b"
|
|
ju 2
|
|
blo "42300,14700"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "b"
|
|
t "signed"
|
|
b "(bitNb-1 downto 0)"
|
|
o 7
|
|
suid 2007,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Alu
|
|
uid 2360,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "30000,14000,46000,22000"
|
|
)
|
|
oxt "32000,15000,48000,23000"
|
|
ttg (MlTextGroup
|
|
uid 2361,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*31 (Text
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uid 2362,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "39600,21800,49100,22700"
|
|
st "pipelinedOperators"
|
|
blo "39600,22500"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*32 (Text
|
|
uid 2363,0
|
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va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "39600,23000,46600,23900"
|
|
st "pipelineAdder"
|
|
blo "39600,23700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*33 (Text
|
|
uid 2364,0
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va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "39600,24200,42100,25100"
|
|
st "I_DUT"
|
|
blo "39600,24900"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 2365,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 2366,0
|
|
text (MLText
|
|
uid 2367,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "40000,25600,59400,27600"
|
|
st "bitNb = adderBitNb ( positive )
|
|
stageNb = pipelineStageNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "bitNb"
|
|
type "positive"
|
|
value "adderBitNb"
|
|
)
|
|
(GiElement
|
|
name "stageNb"
|
|
type "positive"
|
|
value "pipelineStageNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*34 (Wire
|
|
uid 2226,0
|
|
shape (OrthoPolyLine
|
|
uid 2227,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "30000,21000,33917,30000"
|
|
pts [
|
|
"33917,21000"
|
|
"30000,21000"
|
|
"30000,30000"
|
|
]
|
|
)
|
|
start &26
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2230,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2231,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "28917,19600,33017,21000"
|
|
st "reset"
|
|
blo "28917,20800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*35 (Wire
|
|
uid 2234,0
|
|
shape (OrthoPolyLine
|
|
uid 2235,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "28000,20000,33250,30000"
|
|
pts [
|
|
"33250,20000"
|
|
"28000,20000"
|
|
"28000,30000"
|
|
]
|
|
)
|
|
start &25
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2238,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2239,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "28250,18600,32050,20000"
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shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "-50,0,8050,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*63 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,3500,2750,4500"
|
|
st "Library"
|
|
blo "450,4300"
|
|
)
|
|
*64 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,4500,7550,5500"
|
|
st "VerilogComponent"
|
|
blo "450,5300"
|
|
)
|
|
*65 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,5500,1050,6500"
|
|
st "I0"
|
|
blo "450,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6550,1500,-6550,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*66 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,4000,4600,5000"
|
|
st "eb1"
|
|
blo "3400,4800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*67 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,5000,3800,6000"
|
|
st "1"
|
|
blo "3400,5800"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
)
|
|
xt "-300,-500,300,500"
|
|
st "G"
|
|
blo "-300,300"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*68 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*69 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*70 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*71 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5600,6500,6500"
|
|
st "Declarations"
|
|
blo "0,6300"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6500,3000,7400"
|
|
st "Ports:"
|
|
blo "0,7200"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7400,4500,8300"
|
|
st "Pre User:"
|
|
blo "0,8100"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,8300,22100,12300"
|
|
st "constant adderBitNb: positive := 32;
|
|
constant pipelineStageNb: positive := 4;
|
|
constant clockFrequency : real := 60.0E6;
|
|
--constant clockFrequency : real := 66.0E6;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,12300,8500,13200"
|
|
st "Diagram Signals:"
|
|
blo "0,13000"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5600,5500,6500"
|
|
st "Post User:"
|
|
blo "0,6300"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,5600,0,5600"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 24,0
|
|
usingSuid 1
|
|
emptyRow *72 (LEmptyRow
|
|
)
|
|
uid 1321,0
|
|
optionalChildren [
|
|
*73 (RefLabelRowHdr
|
|
)
|
|
*74 (TitleRowHdr
|
|
)
|
|
*75 (FilterRowHdr
|
|
)
|
|
*76 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*77 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*78 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*79 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*80 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*81 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*82 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*83 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*84 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*85 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 18,0
|
|
)
|
|
)
|
|
uid 2272,0
|
|
)
|
|
*86 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 19,0
|
|
)
|
|
)
|
|
uid 2274,0
|
|
)
|
|
*87 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "cOut"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 20,0
|
|
)
|
|
)
|
|
uid 2276,0
|
|
)
|
|
*88 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "cIn"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 21,0
|
|
)
|
|
)
|
|
uid 2278,0
|
|
)
|
|
*89 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "b"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 2
|
|
suid 22,0
|
|
)
|
|
)
|
|
uid 2280,0
|
|
)
|
|
*90 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "a"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
suid 23,0
|
|
)
|
|
)
|
|
uid 2282,0
|
|
)
|
|
*91 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "sum"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 24,0
|
|
)
|
|
)
|
|
uid 2292,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 1334,0
|
|
optionalChildren [
|
|
*92 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *93 (MRCItem
|
|
litem &72
|
|
pos 7
|
|
dimension 20
|
|
)
|
|
uid 1336,0
|
|
optionalChildren [
|
|
*94 (MRCItem
|
|
litem &73
|
|
pos 0
|
|
dimension 20
|
|
uid 1337,0
|
|
)
|
|
*95 (MRCItem
|
|
litem &74
|
|
pos 1
|
|
dimension 23
|
|
uid 1338,0
|
|
)
|
|
*96 (MRCItem
|
|
litem &75
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1339,0
|
|
)
|
|
*97 (MRCItem
|
|
litem &85
|
|
pos 0
|
|
dimension 20
|
|
uid 2273,0
|
|
)
|
|
*98 (MRCItem
|
|
litem &86
|
|
pos 1
|
|
dimension 20
|
|
uid 2275,0
|
|
)
|
|
*99 (MRCItem
|
|
litem &87
|
|
pos 2
|
|
dimension 20
|
|
uid 2277,0
|
|
)
|
|
*100 (MRCItem
|
|
litem &88
|
|
pos 3
|
|
dimension 20
|
|
uid 2279,0
|
|
)
|
|
*101 (MRCItem
|
|
litem &89
|
|
pos 4
|
|
dimension 20
|
|
uid 2281,0
|
|
)
|
|
*102 (MRCItem
|
|
litem &90
|
|
pos 5
|
|
dimension 20
|
|
uid 2283,0
|
|
)
|
|
*103 (MRCItem
|
|
litem &91
|
|
pos 6
|
|
dimension 20
|
|
uid 2293,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1340,0
|
|
optionalChildren [
|
|
*104 (MRCItem
|
|
litem &76
|
|
pos 0
|
|
dimension 20
|
|
uid 1341,0
|
|
)
|
|
*105 (MRCItem
|
|
litem &78
|
|
pos 1
|
|
dimension 50
|
|
uid 1342,0
|
|
)
|
|
*106 (MRCItem
|
|
litem &79
|
|
pos 2
|
|
dimension 100
|
|
uid 1343,0
|
|
)
|
|
*107 (MRCItem
|
|
litem &80
|
|
pos 3
|
|
dimension 50
|
|
uid 1344,0
|
|
)
|
|
*108 (MRCItem
|
|
litem &81
|
|
pos 4
|
|
dimension 100
|
|
uid 1345,0
|
|
)
|
|
*109 (MRCItem
|
|
litem &82
|
|
pos 5
|
|
dimension 100
|
|
uid 1346,0
|
|
)
|
|
*110 (MRCItem
|
|
litem &83
|
|
pos 6
|
|
dimension 50
|
|
uid 1347,0
|
|
)
|
|
*111 (MRCItem
|
|
litem &84
|
|
pos 7
|
|
dimension 80
|
|
uid 1348,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1335,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1320,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *112 (LEmptyRow
|
|
)
|
|
uid 1350,0
|
|
optionalChildren [
|
|
*113 (RefLabelRowHdr
|
|
)
|
|
*114 (TitleRowHdr
|
|
)
|
|
*115 (FilterRowHdr
|
|
)
|
|
*116 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*117 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*118 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*119 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*120 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*121 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*122 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*123 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 1362,0
|
|
optionalChildren [
|
|
*124 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *125 (MRCItem
|
|
litem &112
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 1364,0
|
|
optionalChildren [
|
|
*126 (MRCItem
|
|
litem &113
|
|
pos 0
|
|
dimension 20
|
|
uid 1365,0
|
|
)
|
|
*127 (MRCItem
|
|
litem &114
|
|
pos 1
|
|
dimension 23
|
|
uid 1366,0
|
|
)
|
|
*128 (MRCItem
|
|
litem &115
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1367,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1368,0
|
|
optionalChildren [
|
|
*129 (MRCItem
|
|
litem &116
|
|
pos 0
|
|
dimension 20
|
|
uid 1369,0
|
|
)
|
|
*130 (MRCItem
|
|
litem &118
|
|
pos 1
|
|
dimension 50
|
|
uid 1370,0
|
|
)
|
|
*131 (MRCItem
|
|
litem &119
|
|
pos 2
|
|
dimension 100
|
|
uid 1371,0
|
|
)
|
|
*132 (MRCItem
|
|
litem &120
|
|
pos 3
|
|
dimension 100
|
|
uid 1372,0
|
|
)
|
|
*133 (MRCItem
|
|
litem &121
|
|
pos 4
|
|
dimension 50
|
|
uid 1373,0
|
|
)
|
|
*134 (MRCItem
|
|
litem &122
|
|
pos 5
|
|
dimension 50
|
|
uid 1374,0
|
|
)
|
|
*135 (MRCItem
|
|
litem &123
|
|
pos 6
|
|
dimension 80
|
|
uid 1375,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1363,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1349,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|