1493 lines
19 KiB
Plaintext
1493 lines
19 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 9,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 74,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 7,0
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)
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)
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uid 261,0
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)
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*15 (LogPort
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port (LogicalPort
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decl (Decl
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n "countOut"
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t "unsigned"
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b "(counterBitNb-1 downto 0)"
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o 2
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suid 8,0
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)
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)
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uid 263,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 3
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suid 9,0
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)
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)
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uid 265,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 87,0
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optionalChildren [
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*17 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *18 (MRCItem
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litem &1
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pos 3
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dimension 20
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)
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uid 89,0
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optionalChildren [
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*19 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 90,0
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)
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*20 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 91,0
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)
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*21 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 92,0
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)
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*22 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 262,0
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)
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*23 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 264,0
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)
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*24 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 266,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 93,0
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optionalChildren [
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*25 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 94,0
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)
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*26 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 95,0
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)
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*27 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 96,0
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)
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*28 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 97,0
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)
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*29 (MRCItem
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litem &10
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pos 4
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dimension 100
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uid 98,0
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)
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*30 (MRCItem
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litem &11
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pos 5
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dimension 100
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uid 99,0
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)
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*31 (MRCItem
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litem &12
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pos 6
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dimension 50
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uid 100,0
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)
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*32 (MRCItem
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litem &13
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pos 7
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dimension 80
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uid 101,0
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)
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]
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)
|
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 88,0
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vaOverrides [
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]
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)
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]
|
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)
|
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uid 73,0
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)
|
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genericsCommonDM (CommonDM
|
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ldm (LogicalDM
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emptyRow *33 (LEmptyRow
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)
|
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uid 103,0
|
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optionalChildren [
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*34 (RefLabelRowHdr
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)
|
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*35 (TitleRowHdr
|
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)
|
|
*36 (FilterRowHdr
|
|
)
|
|
*37 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*38 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*39 (GroupColHdr
|
|
tm "GroupColHdrMgr"
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|
)
|
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*40 (NameColHdr
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|
tm "GenericNameColHdrMgr"
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)
|
|
*41 (TypeColHdr
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|
tm "GenericTypeColHdrMgr"
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)
|
|
*42 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*43 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*44 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*45 (LogGeneric
|
|
generic (GiElement
|
|
name "counterBitNb"
|
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type "integer"
|
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value ""
|
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)
|
|
uid 152,0
|
|
)
|
|
*46 (LogGeneric
|
|
generic (GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value ""
|
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)
|
|
uid 221,0
|
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)
|
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]
|
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)
|
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pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 115,0
|
|
optionalChildren [
|
|
*47 (Sheet
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sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
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fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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)
|
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groupVa (MVa
|
|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *48 (MRCItem
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litem &33
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|
pos 2
|
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dimension 20
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)
|
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uid 117,0
|
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optionalChildren [
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*49 (MRCItem
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litem &34
|
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pos 0
|
|
dimension 20
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|
uid 118,0
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)
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*50 (MRCItem
|
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litem &35
|
|
pos 1
|
|
dimension 23
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|
uid 119,0
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)
|
|
*51 (MRCItem
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litem &36
|
|
pos 2
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hidden 1
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|
dimension 20
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uid 120,0
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)
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*52 (MRCItem
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litem &45
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pos 0
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dimension 20
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uid 153,0
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)
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*53 (MRCItem
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litem &46
|
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pos 1
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dimension 20
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uid 222,0
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)
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]
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)
|
|
sheetCol (SheetCol
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|
propVa (MVa
|
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 121,0
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optionalChildren [
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*54 (MRCItem
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litem &37
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pos 0
|
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dimension 20
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uid 122,0
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)
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*55 (MRCItem
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litem &39
|
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pos 1
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dimension 50
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uid 123,0
|
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)
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*56 (MRCItem
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litem &40
|
|
pos 2
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dimension 100
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uid 124,0
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)
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*57 (MRCItem
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litem &41
|
|
pos 3
|
|
dimension 100
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uid 125,0
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)
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*58 (MRCItem
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litem &42
|
|
pos 4
|
|
dimension 50
|
|
uid 126,0
|
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)
|
|
*59 (MRCItem
|
|
litem &43
|
|
pos 5
|
|
dimension 50
|
|
uid 127,0
|
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)
|
|
*60 (MRCItem
|
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litem &44
|
|
pos 6
|
|
dimension 80
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|
uid 128,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 116,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 102,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\@pipeline@counter_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\@pipeline@counter_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\@pipeline@counter_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\PipelineCounter_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "PipelineCounter_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:21:00"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "PipelinedOperators_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/PipelinedOperators_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "PipelineCounter_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\@pipeline@counter_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\PipelineCounter_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "15:21:00"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "PipelineCounter_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 72,0
|
|
optionalChildren [
|
|
*61 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*62 (CptPort
|
|
uid 246,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 247,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "23625,5250,24375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 248,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 249,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
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|
)
|
|
xt "23300,7000,24700,10800"
|
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ps "TopLeftStrategy"
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text (Text
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va (VaSet
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font "Verdana,9,1"
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)
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blo "1000,2000"
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tm "PanelText"
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)
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parentGraphicsRef (HdmGraphicsRef
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libraryName "PipelinedOperators_test"
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entityName "pipelineCounter_tb"
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viewName "struct.bd"
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defaultSymbolBody (SymbolBody
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shape (Rectangle
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va (VaSet
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lineColor "0,32896,0"
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biTextGroup (BiTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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)
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blo "26800,17000"
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gi *80 (GenericInterface
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ps "CenterOffsetStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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elements [
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portInstanceVis (PortSigDisplay
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sIVOD 1
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)
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portVis (PortSigDisplay
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sIVOD 1
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)
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defaultCptPort (CptPort
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 90
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va (VaSet
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vasetType 1
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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)
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tm "CptPortNameMgr"
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va (VaSet
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tg (CPTG
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stg "VerticalLayoutStrategy"
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blo "0,1950"
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tm "CptPortNameMgr"
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va (VaSet
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thePort (LogicalPort
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decl (Decl
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)
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DeclarativeBlock *81 (SymDeclBlock
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uid 1,0
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stg "SymDeclLayoutStrategy"
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declLabel (Text
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uid 2,0
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va (VaSet
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font "Verdana,9,1"
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)
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portLabel (Text
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va (VaSet
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font "Verdana,9,1"
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xt "42000,1200,45700,2400"
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externalLabel (Text
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xt "42000,4800,45200,6000"
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blo "42000,5800"
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)
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internalLabel (Text
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va (VaSet
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font "Verdana,9,1"
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)
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xt "42000,0,50200,1200"
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blo "42000,1000"
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)
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externalText (MLText
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va (VaSet
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font "Courier New,8,0"
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tm "SyDeclarativeTextMgr"
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)
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internalText (MLText
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uid 7,0
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va (VaSet
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isHidden 1
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font "Courier New,8,0"
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)
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xt "42000,0,42000,0"
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tm "SyDeclarativeTextMgr"
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)
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)
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)
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