1723 lines
22 KiB
Plaintext
1723 lines
22 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 2006,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 163,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "triggerOut"
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t "std_ulogic"
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o 3
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suid 3,0
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)
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)
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uid 165,0
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)
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*3 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "xOut"
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t "std_ulogic"
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o 4
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suid 4,0
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)
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)
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uid 166,0
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)
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*4 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "yOut"
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t "std_ulogic"
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o 5
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suid 5,0
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)
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)
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uid 167,0
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)
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*5 (LogPort
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port (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 1,0
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)
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)
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uid 168,0
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)
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*6 (RefLabelRowHdr
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)
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*7 (TitleRowHdr
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)
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|
*8 (FilterRowHdr
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)
|
|
*9 (RefLabelColHdr
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|
tm "RefLabelColHdrMgr"
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)
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|
*10 (RowExpandColHdr
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|
tm "RowExpandColHdrMgr"
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)
|
|
*11 (GroupColHdr
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|
tm "GroupColHdrMgr"
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)
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|
*12 (NameColHdr
|
|
tm "NameColHdrMgr"
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)
|
|
*13 (ModeColHdr
|
|
tm "ModeColHdrMgr"
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)
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|
*14 (TypeColHdr
|
|
tm "TypeColHdrMgr"
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)
|
|
*15 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
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)
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|
*16 (InitColHdr
|
|
tm "InitColHdrMgr"
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)
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|
*17 (EolColHdr
|
|
tm "EolColHdrMgr"
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)
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|
*18 (LogPort
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port (LogicalPort
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|
decl (Decl
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|
n "reset"
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|
t "std_ulogic"
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o 2
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suid 2006,0
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)
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)
|
|
uid 427,0
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|
)
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]
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)
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pdm (PhysicalDM
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|
displayShortBounds 1
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|
editShortBounds 1
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|
uid 169,0
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|
optionalChildren [
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|
*19 (Sheet
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|
sheetRow (SheetRow
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|
headerVa (MVa
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|
cellColor "49152,49152,49152"
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|
fontColor "0,0,0"
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|
font "courier,10,0"
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)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
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|
font "courier,10,0"
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)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *20 (MRCItem
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litem &1
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pos 5
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dimension 20
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)
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uid 104,0
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optionalChildren [
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*21 (MRCItem
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litem &6
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pos 0
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dimension 20
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uid 107,0
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)
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*22 (MRCItem
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litem &7
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pos 1
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dimension 23
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uid 109,0
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)
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*23 (MRCItem
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litem &8
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pos 2
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hidden 1
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dimension 20
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uid 111,0
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)
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*24 (MRCItem
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litem &2
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pos 1
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dimension 20
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uid 131,0
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)
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*25 (MRCItem
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litem &3
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pos 2
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dimension 20
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uid 132,0
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)
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*26 (MRCItem
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litem &4
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pos 3
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dimension 20
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uid 133,0
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)
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*27 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 134,0
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)
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*28 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 426,0
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)
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]
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)
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sheetCol (SheetCol
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|
propVa (MVa
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|
cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
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uid 105,0
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optionalChildren [
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*29 (MRCItem
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litem &9
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pos 0
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dimension 20
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uid 113,0
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)
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*30 (MRCItem
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litem &11
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pos 1
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dimension 50
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uid 117,0
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)
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*31 (MRCItem
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|
litem &12
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pos 2
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dimension 100
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|
uid 119,0
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)
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*32 (MRCItem
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litem &13
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pos 3
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dimension 50
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uid 121,0
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)
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|
*33 (MRCItem
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litem &14
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pos 4
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dimension 100
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|
uid 123,0
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)
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*34 (MRCItem
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|
litem &15
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pos 5
|
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dimension 100
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|
uid 125,0
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)
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*35 (MRCItem
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|
litem &16
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pos 6
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|
dimension 50
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|
uid 127,0
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)
|
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*36 (MRCItem
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|
litem &17
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|
pos 7
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|
dimension 80
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|
uid 129,0
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)
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]
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)
|
|
fixedCol 4
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fixedRow 2
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name "Ports"
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uid 103,0
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|
vaOverrides [
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|
]
|
|
)
|
|
]
|
|
)
|
|
uid 162,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *37 (LEmptyRow
|
|
)
|
|
uid 171,0
|
|
optionalChildren [
|
|
*38 (RefLabelRowHdr
|
|
)
|
|
*39 (TitleRowHdr
|
|
)
|
|
*40 (FilterRowHdr
|
|
)
|
|
*41 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*42 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*43 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*44 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*45 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*46 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*47 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*48 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*49 (LogGeneric
|
|
generic (GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 160,0
|
|
)
|
|
*50 (LogGeneric
|
|
generic (GiElement
|
|
name "phaseBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 479,0
|
|
)
|
|
*51 (LogGeneric
|
|
generic (GiElement
|
|
name "stepX"
|
|
type "positive"
|
|
value "1"
|
|
)
|
|
uid 481,0
|
|
)
|
|
*52 (LogGeneric
|
|
generic (GiElement
|
|
name "stepY"
|
|
type "positive"
|
|
value "1"
|
|
)
|
|
uid 483,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 172,0
|
|
optionalChildren [
|
|
*53 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *54 (MRCItem
|
|
litem &37
|
|
pos 4
|
|
dimension 20
|
|
)
|
|
uid 136,0
|
|
optionalChildren [
|
|
*55 (MRCItem
|
|
litem &38
|
|
pos 0
|
|
dimension 20
|
|
uid 139,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &39
|
|
pos 1
|
|
dimension 23
|
|
uid 141,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &40
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 143,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &49
|
|
pos 0
|
|
dimension 20
|
|
uid 161,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &50
|
|
pos 1
|
|
dimension 20
|
|
uid 480,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &51
|
|
pos 2
|
|
dimension 20
|
|
uid 482,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &52
|
|
pos 3
|
|
dimension 20
|
|
uid 484,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 137,0
|
|
optionalChildren [
|
|
*62 (MRCItem
|
|
litem &41
|
|
pos 0
|
|
dimension 20
|
|
uid 145,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &43
|
|
pos 1
|
|
dimension 50
|
|
uid 149,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
dimension 100
|
|
uid 151,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &45
|
|
pos 3
|
|
dimension 100
|
|
uid 153,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &46
|
|
pos 4
|
|
dimension 50
|
|
uid 155,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &47
|
|
pos 5
|
|
dimension 50
|
|
uid 157,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &48
|
|
pos 6
|
|
dimension 80
|
|
uid 159,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 135,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 170,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hds/lissajous@generator/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hds/lissajous@generator/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hds/lissajous@generator"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hds/lissajousGenerator"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "02/19/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Tue"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Tuesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "19"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "lissajousGenerator"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "02/19/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:07:53"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Lissajous"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../Board/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Lissajous"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "02"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "lissajousGenerator"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Feb"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "February"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hds/lissajous@generator/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Lissajous/hds/lissajousGenerator/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "lissajous"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:07:53"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "lissajousGenerator"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 51,0
|
|
optionalChildren [
|
|
*69 (SymbolBody
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|
uid 8,0
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optionalChildren [
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|
*70 (CptPort
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uid 52,0
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ps "OnEdgeStrategy"
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shape (Triangle
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va (VaSet
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fg "0,65535,0"
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|
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|
|
xt "31250,17625,32000,18375"
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|
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tg (CPTG
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uid 54,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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st "clock"
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blo "33000,18100"
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tm "CptPortNameMgr"
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st "clock : IN std_ulogic ;"
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)
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thePort (LogicalPort
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decl (Decl
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|
n "clock"
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t "std_ulogic"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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blo "47000,18100"
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tm "CptPortNameMgr"
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decl (Decl
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)
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*72 (CptPort
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ps "OnEdgeStrategy"
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va (VaSet
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tg (CPTG
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font "courier,9,0"
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|
blo "47000,16100"
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tm "CptPortNameMgr"
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dt (MLText
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font "courier,8,0"
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)
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xt "2000,13500,19000,14400"
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|
st "xOut : OUT std_ulogic ;"
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|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "xOut"
|
|
t "std_ulogic"
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|
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|
|
suid 4,0
|
|
)
|
|
)
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)
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*73 (CptPort
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uid 98,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 99,0
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va (VaSet
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vasetType 1
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tg (CPTG
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|
uid 100,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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va (VaSet
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font "courier,9,0"
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st "yOut"
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ju 2
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blo "47000,14100"
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tm "CptPortNameMgr"
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font "courier,8,0"
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)
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|
st "yOut : OUT std_ulogic "
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "yOut"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*74 (CptPort
|
|
uid 428,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 429,0
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ro 90
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va (VaSet
|
|
vasetType 1
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fg "0,65535,0"
|
|
)
|
|
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|
|
)
|
|
tg (CPTG
|
|
uid 430,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 431,0
|
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va (VaSet
|
|
)
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|
xt "33000,19500,36000,20500"
|
|
st "reset"
|
|
blo "33000,20300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
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dt (MLText
|
|
uid 432,0
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va (VaSet
|
|
font "courier,8,0"
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|
)
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|
xt "2000,11700,19000,12600"
|
|
st "reset : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
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|
|
suid 2006,0
|
|
)
|
|
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|
)
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|
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uid 81,0
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va (VaSet
|
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vasetType 1
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bg "0,65535,0"
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|
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lineWidth 2
|
|
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|
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biTextGroup (BiTextGroup
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uid 10,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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first (Text
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va (VaSet
|
|
font "courier,9,1"
|
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)
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|
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|
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|
|
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|
|
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second (Text
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|
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va (VaSet
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|
font "courier,9,1"
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|
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|
|
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|
|
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|
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gi *75 (GenericInterface
|
|
uid 13,0
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ps "CenterOffsetStrategy"
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text (MLText
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va (VaSet
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font "courier,8,0"
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|
st "Generic Declarations
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|
|
|
signalBitNb positive 16
|
|
phaseBitNb positive 16
|
|
stepX positive 1
|
|
stepY positive 1
|
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|
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header "Generic Declarations"
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showHdrWhenContentsEmpty 1
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elements [
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|
|
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|
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|
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|
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|
|
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|
|
type "positive"
|
|
value "1"
|
|
)
|
|
(GiElement
|
|
name "stepY"
|
|
type "positive"
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|
value "1"
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|
)
|
|
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|
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portInstanceVisAsIs 1
|
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portInstanceVis (PortSigDisplay
|
|
sTC 0
|
|
)
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portVis (PortSigDisplay
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|
sTC 0
|
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sF 0
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