21 lines
524 B
VHDL
21 lines
524 B
VHDL
ARCHITECTURE bhv OF bram IS
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type ramContentType is array(2**addressBitNb-1 downto 0) of std_logic_vector(dataBitNb-1 DOWNTO 0);
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shared variable ramContent: ramContentType ;
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BEGIN
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process(clock)
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begin
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if rising_edge(clock) then
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if en = '1' then
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if writeEn = '1' then
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ramContent(to_integer(unsigned(addressIn))) := dataIn;
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end if;
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dataOut <= ramContent(to_integer(unsigned(addressIn)));
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end if;
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end if;
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end process;
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END ARCHITECTURE bhv;
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