38 lines
1.0 KiB
Plaintext
38 lines
1.0 KiB
Plaintext
-- VHDL Entity AhbLiteComponents_test.ahbUart_tester.interface
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--
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-- Created:
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-- by - zas.UNKNOWN (ZELL)
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-- at - 17:08:42 02/17/2020
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY AhbLite;
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USE AhbLite.ahbLite.all;
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ENTITY ahbUart_tester IS
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GENERIC(
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clockFrequency : real
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);
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PORT(
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TxD : IN std_ulogic;
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hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hReady : IN std_uLogic;
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hResp : IN std_uLogic;
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RxD : OUT std_ulogic;
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hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
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hClk : OUT std_uLogic;
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hReset_n : OUT std_uLogic;
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hSel : OUT std_uLogic;
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hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
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hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hWrite : OUT std_uLogic
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);
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-- Declarations
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END ahbUart_tester ;
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