38 lines
1.1 KiB
Plaintext
38 lines
1.1 KiB
Plaintext
-- VHDL Entity AhbLiteComponents_test.ahbGpio_tester.interface
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 14:51:40 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY AhbLite;
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USE AhbLite.ahbLite.all;
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ENTITY ahbGpio_tester IS
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GENERIC(
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ioNb : positive;
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clockFrequency : real
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);
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PORT(
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hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hReady : IN std_uLogic;
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hResp : IN std_uLogic;
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hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
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hClk : OUT std_uLogic;
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hReset_n : OUT std_uLogic;
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hSel : OUT std_uLogic;
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hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
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hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hWrite : OUT std_uLogic;
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io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
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);
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-- Declarations
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END ahbGpio_tester ;
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