149 lines
4.5 KiB
Plaintext
149 lines
4.5 KiB
Plaintext
--
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-- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct
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--
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-- Created:
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-- by - remi.heredero.UNKNOWN (WE2330808)
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-- at - 14:16:25 19.04.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY AhbLite;
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USE AhbLite.ahbLite.all;
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LIBRARY AhbLiteComponents;
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LIBRARY AhbLiteComponents_test;
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ARCHITECTURE struct OF ahbGpio_tb IS
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-- Architecture declarations
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constant ioNb: positive := 8;
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constant clockFrequency : real := 60.0E6;
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--constant clockFrequency : real := 66.0E6;
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-- Internal signal declarations
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SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
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SIGNAL hClk : std_uLogic;
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SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
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SIGNAL hReady : std_uLogic;
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SIGNAL hReset_n : std_uLogic;
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SIGNAL hResp : std_uLogic;
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SIGNAL hSel : std_uLogic;
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SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
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SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
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SIGNAL hWrite : std_uLogic;
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SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0);
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SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0);
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SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0);
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SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0);
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-- Component Declarations
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COMPONENT ahbGpio
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GENERIC (
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ioNb : positive := 8
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);
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PORT (
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hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
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hClk : IN std_uLogic ;
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hReset_n : IN std_uLogic ;
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hSel : IN std_uLogic ;
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hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
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hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hWrite : IN std_uLogic ;
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ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0);
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hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hReady : OUT std_uLogic ;
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hResp : OUT std_uLogic ;
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ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0);
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ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT ahbGpio_tester
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GENERIC (
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ioNb : positive;
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clockFrequency : real
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);
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PORT (
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hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hReady : IN std_uLogic ;
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hResp : IN std_uLogic ;
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hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
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hClk : OUT std_uLogic ;
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hReset_n : OUT std_uLogic ;
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hSel : OUT std_uLogic ;
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hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
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hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hWrite : OUT std_uLogic ;
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io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : ahbGpio USE ENTITY AhbLiteComponents.ahbGpio;
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FOR ALL : ahbGpio_tester USE ENTITY AhbLiteComponents_test.ahbGpio_tester;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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tristate: process(ioEn, ioOut)
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begin
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for index in io'range loop
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if ioEn(index) = '1' then
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io(index) <= ioOut(index);
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else
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io(index) <= 'Z';
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end if;
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end loop;
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end process tristate;
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ioIn <= std_ulogic_vector(io);
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-- Instance port mappings.
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I_DUT : ahbGpio
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GENERIC MAP (
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ioNb => ioNb
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)
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PORT MAP (
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hAddr => hAddr,
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hClk => hClk,
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hReset_n => hReset_n,
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hSel => hSel,
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hTrans => hTrans,
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hWData => hWData,
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hWrite => hWrite,
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ioIn => ioIn,
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hRData => hRData,
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hReady => hReady,
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hResp => hResp,
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ioEn => ioEn,
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ioOut => ioOut
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);
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I_tester : ahbGpio_tester
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GENERIC MAP (
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ioNb => ioNb,
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clockFrequency => clockFrequency
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)
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PORT MAP (
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hRData => hRData,
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hReady => hReady,
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hResp => hResp,
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hAddr => hAddr,
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hClk => hClk,
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hReset_n => hReset_n,
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hSel => hSel,
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hTrans => hTrans,
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hWData => hWData,
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hWrite => hWrite,
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io => io
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);
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END struct;
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