38 lines
966 B
VHDL
38 lines
966 B
VHDL
ARCHITECTURE studentVersion OF triangleToPolygon IS
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signal mySignal : unsigned(bitNb downto 0);
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constant aFullTriangle : unsigned(bitNb downto 0) := (others => '1');
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signal bigTriangle: unsigned(bitNb downto 0);
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signal oneOfHeight: unsigned(bitNb downto 0);
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signal fiveOfHeight: unsigned(bitNb downto 0);
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BEGIN
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resizeTriangle: process(triangle)
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begin
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bigTriangle <= ('0' & triangle) + ('0' & shift_right(triangle, 1));
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oneOfHeight <= shift_right(aFullTriangle, 3);
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fiveOfHeight <= shift_right(aFullTriangle, 1) + shift_right(aFullTriangle, 3);
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end process resizeTriangle;
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convert: process(bigTriangle)
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begin
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if bigTriangle < oneOfHeight then
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mySignal <= oneOfHeight;
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elsif bigTriangle > fiveOfHeight then
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mySignal <= fiveOfHeight;
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else
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mySignal <= bigTriangle;
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end if ;
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end process convert;
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polygon <= resize(mySignal-oneOfHeight, bitNb);
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END ARCHITECTURE studentVersion;
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