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base: Klagarge:SoC
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Klagarge:main Klagarge:SoC Klagarge:morse Klagarge:interpolation-with-math
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compare: Klagarge:morse
Branches Tags
Klagarge:SoC Klagarge:morse Klagarge:main Klagarge:interpolation-with-math

1 Commits
SoC ... morse

Author SHA1 Message Date
Klagarge
14f542a674 - 2024-04-17 12:50:48 +02:00
36 changed files with 744 additions and 12767 deletions
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33
05-Morse/Morse/hdl/charToMorseController_studentVersion.vhd
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@@ -94,6 +94,15 @@ BEGIN
process(reset, clock) begin process(reset, clock) begin
if reset = '1' then
register1 <= SPACE;
register2 <= SPACE;
register3 <= SPACE;
register4 <= SPACE;
register5 <= SPACE;
signSendRegisters <= '0';
elsif rising_edge(clock) then
case general_current_state is case general_current_state is
when waitForChar => when waitForChar =>
--report "General current state is wait for char" severity note; --report "General current state is wait for char" severity note;
@@ -339,9 +348,11 @@ BEGIN
--report "General current state is send registers" severity note; --report "General current state is send registers" severity note;
readChar <= '0'; readChar <= '0';
signSendRegisters <= '0'; signSendRegisters <= '0';
if signRegistersSended then if signRegistersSended = '1' then
general_next_state <= sended; general_next_state <= sended;
report "Char is send" severity note; report "Char is send" severity note;
else
general_next_state <= sendRegisters;
end if; end if;
when sended => when sended =>
@@ -358,9 +369,18 @@ BEGIN
general_next_state <= waitForChar; general_next_state <= waitForChar;
end case; end case;
end if;
end process; end process;
process(reset, clock) begin process(reset, clock) begin
if reset = '1' then
morseOut <= '0';
startCounter <= '0';
unitNb <= "000";
signRegistersSended <= '0';
elsif rising_edge(clock) then
case sending_current_state is case sending_current_state is
when waiting => when waiting =>
@@ -376,7 +396,7 @@ BEGIN
end if; end if;
when sendR1 => when sendR1 =>
report "Send register1" severity note; --report "Send register1" severity note;
startCounter <= '1'; startCounter <= '1';
morseOut <= '1'; morseOut <= '1';
case register1 is case register1 is
@@ -398,7 +418,7 @@ BEGIN
end case; end case;
when waitR1 => when waitR1 =>
report "Wait register1" severity note; --report "Wait register1" severity note;
startCounter <= '0'; startCounter <= '0';
if counterDone = '1' then if counterDone = '1' then
morseOut <= '0'; morseOut <= '0';
@@ -406,7 +426,7 @@ BEGIN
end if; end if;
when sendR2 => when sendR2 =>
report "Send register2" severity note; --report "Send register2" severity note;
startCounter <= '1'; startCounter <= '1';
morseOut <= '1'; morseOut <= '1';
case register2 is case register2 is
@@ -428,7 +448,7 @@ BEGIN
end case; end case;
when waitR2 => when waitR2 =>
report "Wait register2" severity note; --report "Wait register2" severity note;
startCounter <= '0'; startCounter <= '0';
if counterDone = '1' then if counterDone = '1' then
morseOut <= '0'; morseOut <= '0';
@@ -436,7 +456,7 @@ BEGIN
end if; end if;
when sendR3 => when sendR3 =>
report "Send register3" severity note; --report "Send register3" severity note;
startCounter <= '1'; startCounter <= '1';
morseOut <= '1'; morseOut <= '1';
case register3 is case register3 is
@@ -520,6 +540,7 @@ BEGIN
sending_next_state <= waiting; sending_next_state <= waiting;
end case; end case;
end if;
end process; end process;

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05-Morse/Morse/hds/.cache.dat
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05-Morse/Morse_test/hds/.cache.dat
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109
06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd
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@@ -18,123 +18,16 @@
-- 00, data register provides the values detected on the lines. -- 00, data register provides the values detected on the lines.
-- --
ARCHITECTURE studentVersion OF ahbGpio IS ARCHITECTURE studentVersion OF ahbGpio IS
signal addresses: unsigned(hAddr'range);
signal bRead: std_ulogic;
signal bWrite: std_ulogic;
signal bDone: std_ulogic;
BEGIN BEGIN
process(hReset_n, hClk) begin
if hReset_n = '0' then
-- AHB-Lite -- AHB-Lite
--hRData <= (OTHERS => 'Z');
hRData <= (OTHERS => '0'); hRData <= (OTHERS => '0');
hReady <= '1'; hReady <= '0';
hResp <= '0'; hResp <= '0';
-- Out -- Out
ioOut <= (OTHERS => '0'); ioOut <= (OTHERS => '0');
ioEn <= (OTHERS => '0'); ioEn <= (OTHERS => '0');
addresses <= (OTHERS => '0');
bRead <= '0';
bWrite <= '0';
bDone <= '0';
elsif rising_edge(hClk) then
if hSel = '1' then
bWrite <= hWrite;
bRead <= not hWrite;
addresses <= hAddr;
hReady <= '0';
bDone <= '0';
else
bWrite <= '0';
bRead <= '0';
end if;
if bRead = '1' and bWrite = '0' then
-------------------------------------------------------------------------
-- READ
-------------------------------------------------------------------------
if addresses = "00" then
-- ##### Read data register #####
--hRData <= unsigned(resize(ioIn, ioNb));
for i in 0 to ioNb-1 loop
hRData(i) <= ioIn(i);
end loop;
bDone <= '1';
elsif addresses = "01" then
report "@@@@@@@@@@ Not possible to change output in READ mode @@@@@@@@@@" severity error;
end if;
elsif bRead = '0' and bWrite = '1' then
-------------------------------------------------------------------------
-- WRITE
-------------------------------------------------------------------------
if addresses = "00" then
-- ##### Write data register #####
--ioOut <= resize(std_ulogic_vector(hWData), ioNb);
for i in 0 to ioNb-1 loop
ioOut(i) <= hWData(i);
end loop;
bDone <= '1';
elsif addresses = "01" then
-- ##### Write direction register #####
--ioEn <= hWData;
for i in 0 to ioNb-1 loop
ioEn(i) <= hWData(i);
end loop;
bDone <= '1';
end if;
elsif bRead = '1' and bWrite = '1' then
-------------------------------------------------------------------------
-- SHOULD NEVER HAPPEN
-------------------------------------------------------------------------
report "@@@@@@@@@@ READ and WRITE can't happened in same time @@@@@@@@@@" severity error;
end if;
if (ioIn and ioEn) = (ioEn and ioOut) then
hResp <= '0';
else
hResp <= '1';
end if;
if bDone = '1' then
--hRData <= (OTHERS => 'Z');
bDone <= '0';
hReady <= '1';
end if;
end if;
for i in (ioNb-1) downto 0 loop
if (ioEn(i) and ioIn(i)) /= (ioEn(i) and ioOut(i)) then
--ioEn(i) <= '0';
report "an output was in conflict" severity note;
end if;
end loop;
end process;
-- AHB-Lite
-- hRData <= (OTHERS => '0');
-- hReady <= '0';
-- hResp <= '0';
-- Out
-- ioOut <= (OTHERS => '0');
-- ioEn <= (OTHERS => '0');
END ARCHITECTURE studentVersion; END ARCHITECTURE studentVersion;

38
06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbgpio_entity.vhg
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@@ -1,38 +0,0 @@
-- VHDL Entity AhbLiteComponents.ahbGpio.symbol
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 15:08:33 23.02.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;
ENTITY ahbGpio IS
GENERIC(
ioNb : positive := 8
);
PORT(
hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : IN std_uLogic;
hReset_n : IN std_uLogic;
hSel : IN std_uLogic;
hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : IN std_uLogic;
ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0);
hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : OUT std_uLogic;
hResp : OUT std_uLogic;
ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0);
ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0)
);
-- Declarations
END ahbGpio ;

38
06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbuart_entity.vhg
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@@ -1,38 +0,0 @@
-- VHDL Entity AhbLiteComponents.ahbUart.symbol
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 15:08:33 23.02.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;
ENTITY ahbUart IS
GENERIC(
txFifoDepth : positive := 8;
rxFifoDepth : positive := 1
);
PORT(
RxD : IN std_ulogic;
hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : IN std_uLogic;
hReset_n : IN std_uLogic;
hSel : IN std_uLogic;
hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : IN std_uLogic;
TxD : OUT std_ulogic;
hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : OUT std_uLogic;
hResp : OUT std_uLogic
);
-- Declarations
END ahbUart ;

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06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat
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54
06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbgpio_entity.xrf
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@@ -1,54 +0,0 @@
DESIGN ahb@gpio
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 104,0 8 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 13,0 15 1
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2452,0 19 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2514,0 20 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2519,0 21 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2692,0 22 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2494,0 23 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2464,0 24 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2474,0 25 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2839,0 26 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2469,0 27 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2504,0 28 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2509,0 29 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2846,0 30 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2651,0 31 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 1,0 34 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 1,0 35 0

51
06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbuart_entity.xrf
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@@ -1,51 +0,0 @@
DESIGN ahb@uart
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 104,0 8 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 13,0 15 1
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2839,0 20 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2452,0 21 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2514,0 22 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2519,0 23 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2692,0 24 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2494,0 25 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2464,0 26 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2474,0 27 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2651,0 28 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2469,0 29 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2504,0 30 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2509,0 31 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 1,0 34 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 1,0 35 0

15
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_entity.vhg
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@@ -1,15 +0,0 @@
-- VHDL Entity AhbLiteComponents_test.ahbGpio_tb.symbol
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:51:39 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY ahbGpio_tb IS
-- Declarations
END ahbGpio_tb ;

148
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg
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@@ -1,148 +0,0 @@
--
-- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 14:16:25 19.04.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;
LIBRARY AhbLiteComponents;
LIBRARY AhbLiteComponents_test;
ARCHITECTURE struct OF ahbGpio_tb IS
-- Architecture declarations
constant ioNb: positive := 8;
constant clockFrequency : real := 60.0E6;
--constant clockFrequency : real := 66.0E6;
-- Internal signal declarations
SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
SIGNAL hClk : std_uLogic;
SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
SIGNAL hReady : std_uLogic;
SIGNAL hReset_n : std_uLogic;
SIGNAL hResp : std_uLogic;
SIGNAL hSel : std_uLogic;
SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
SIGNAL hWrite : std_uLogic;
SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0);
SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0);
SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0);
SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT ahbGpio
GENERIC (
ioNb : positive := 8
);
PORT (
hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : IN std_uLogic ;
hReset_n : IN std_uLogic ;
hSel : IN std_uLogic ;
hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : IN std_uLogic ;
ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0);
hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : OUT std_uLogic ;
hResp : OUT std_uLogic ;
ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0);
ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT ahbGpio_tester
GENERIC (
ioNb : positive;
clockFrequency : real
);
PORT (
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : IN std_uLogic ;
hResp : IN std_uLogic ;
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : OUT std_uLogic ;
hReset_n : OUT std_uLogic ;
hSel : OUT std_uLogic ;
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : OUT std_uLogic ;
io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : ahbGpio USE ENTITY AhbLiteComponents.ahbGpio;
FOR ALL : ahbGpio_tester USE ENTITY AhbLiteComponents_test.ahbGpio_tester;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
tristate: process(ioEn, ioOut)
begin
for index in io'range loop
if ioEn(index) = '1' then
io(index) <= ioOut(index);
else
io(index) <= 'Z';
end if;
end loop;
end process tristate;
ioIn <= std_ulogic_vector(io);
-- Instance port mappings.
I_DUT : ahbGpio
GENERIC MAP (
ioNb => ioNb
)
PORT MAP (
hAddr => hAddr,
hClk => hClk,
hReset_n => hReset_n,
hSel => hSel,
hTrans => hTrans,
hWData => hWData,
hWrite => hWrite,
ioIn => ioIn,
hRData => hRData,
hReady => hReady,
hResp => hResp,
ioEn => ioEn,
ioOut => ioOut
);
I_tester : ahbGpio_tester
GENERIC MAP (
ioNb => ioNb,
clockFrequency => clockFrequency
)
PORT MAP (
hRData => hRData,
hReady => hReady,
hResp => hResp,
hAddr => hAddr,
hClk => hClk,
hReset_n => hReset_n,
hSel => hSel,
hTrans => hTrans,
hWData => hWData,
hWrite => hWrite,
io => io
);
END struct;

37
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tester_entity.vhg
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@@ -1,37 +0,0 @@
-- VHDL Entity AhbLiteComponents_test.ahbGpio_tester.interface
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:51:40 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;
ENTITY ahbGpio_tester IS
GENERIC(
ioNb : positive;
clockFrequency : real
);
PORT(
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : IN std_uLogic;
hResp : IN std_uLogic;
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : OUT std_uLogic;
hReset_n : OUT std_uLogic;
hSel : OUT std_uLogic;
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : OUT std_uLogic;
io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
);
-- Declarations
END ahbGpio_tester ;

15
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_entity.vhg
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@@ -1,15 +0,0 @@
-- VHDL Entity AhbLiteComponents_test.ahbUart_tb.symbol
--
-- Created:
-- by - zas.UNKNOWN (ZELL)
-- at - 17:08:42 02/17/2020
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY ahbUart_tb IS
-- Declarations
END ahbUart_tb ;

132
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_struct.vhg
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@@ -1,132 +0,0 @@
--
-- VHDL Architecture AhbLiteComponents_test.ahbUart_tb.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 15:07:00 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;
LIBRARY AhbLiteComponents;
LIBRARY AhbLiteComponents_test;
ARCHITECTURE struct OF ahbUart_tb IS
-- Architecture declarations
constant txFifoDepth: positive := 1;
constant rxFifoDepth: positive := 1;
constant clockFrequency : real := 60.0E6;
--constant clockFrequency : real := 66.0E6;
-- Internal signal declarations
SIGNAL RxD : std_ulogic;
SIGNAL TxD : std_ulogic;
SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
SIGNAL hClk : std_uLogic;
SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
SIGNAL hReady : std_uLogic;
SIGNAL hReset_n : std_uLogic;
SIGNAL hResp : std_uLogic;
SIGNAL hSel : std_uLogic;
SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
SIGNAL hWrite : std_uLogic;
-- Component Declarations
COMPONENT ahbUart
GENERIC (
txFifoDepth : positive := 8;
rxFifoDepth : positive := 1
);
PORT (
RxD : IN std_ulogic ;
hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : IN std_uLogic ;
hReset_n : IN std_uLogic ;
hSel : IN std_uLogic ;
hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : IN std_uLogic ;
TxD : OUT std_ulogic ;
hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : OUT std_uLogic ;
hResp : OUT std_uLogic
);
END COMPONENT;
COMPONENT ahbUart_tester
GENERIC (
clockFrequency : real
);
PORT (
TxD : IN std_ulogic ;
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : IN std_uLogic ;
hResp : IN std_uLogic ;
RxD : OUT std_ulogic ;
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : OUT std_uLogic ;
hReset_n : OUT std_uLogic ;
hSel : OUT std_uLogic ;
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : OUT std_uLogic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : ahbUart USE ENTITY AhbLiteComponents.ahbUart;
FOR ALL : ahbUart_tester USE ENTITY AhbLiteComponents_test.ahbUart_tester;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I_DUT : ahbUart
GENERIC MAP (
txFifoDepth => txFifoDepth,
rxFifoDepth => rxFifoDepth
)
PORT MAP (
RxD => RxD,
hAddr => hAddr,
hClk => hClk,
hReset_n => hReset_n,
hSel => hSel,
hTrans => hTrans,
hWData => hWData,
hWrite => hWrite,
TxD => TxD,
hRData => hRData,
hReady => hReady,
hResp => hResp
);
I_tester : ahbUart_tester
GENERIC MAP (
clockFrequency => clockFrequency
)
PORT MAP (
TxD => TxD,
hRData => hRData,
hReady => hReady,
hResp => hResp,
RxD => RxD,
hAddr => hAddr,
hClk => hClk,
hReset_n => hReset_n,
hSel => hSel,
hTrans => hTrans,
hWData => hWData,
hWrite => hWrite
);
END struct;

37
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tester_entity.vhg
View File

@@ -1,37 +0,0 @@
-- VHDL Entity AhbLiteComponents_test.ahbUart_tester.interface
--
-- Created:
-- by - zas.UNKNOWN (ZELL)
-- at - 17:08:42 02/17/2020
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;
ENTITY ahbUart_tester IS
GENERIC(
clockFrequency : real
);
PORT(
TxD : IN std_ulogic;
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : IN std_uLogic;
hResp : IN std_uLogic;
RxD : OUT std_ulogic;
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : OUT std_uLogic;
hReset_n : OUT std_uLogic;
hSel : OUT std_uLogic;
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : OUT std_uLogic
);
-- Declarations
END ahbUart_tester ;

BIN
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat
View File

Binary file not shown.

2
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf
View File

@@ -1 +1 @@
DIALECT atom VHDL_2008 DIALECT atom VHDL_ANY

2
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf
View File

@@ -1 +1 @@
DIALECT atom VHDL_2008 DIALECT atom VHDL_ANY

12
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_entity.xrf
View File

@@ -1,12 +0,0 @@
DESIGN ahb@gpio_tb
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN ahb@gpio_tb
VIEW symbol.sb
GRAPHIC 53,0 8 0
DESIGN ahb@gpio_tb
VIEW symbol.sb
GRAPHIC 1,0 11 0
DESIGN ahb@gpio_tb
VIEW symbol.sb
GRAPHIC 1,0 12 0

228
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_struct.xrf
View File

@@ -1,228 +0,0 @@
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 187,0 9 0
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 14
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 0,0 18 2
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 1,0 21 0
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 21
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12627,0 27 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12563,0 28 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12587,0 29 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12579,0 30 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12555,0 31 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12571,0 32 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12595,0 33 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12611,0 34 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12619,0 35 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12603,0 36 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13244,0 37 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13210,0 38 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13226,0 39 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13218,0 40 0
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 41
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 42
LIBRARY AhbLiteComponents
DESIGN ahb@gpio
VIEW student@version
GRAPHIC 13194,0 44 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 14,0 45 1
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2452,0 49 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2514,0 50 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2519,0 51 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2692,0 52 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2494,0 53 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2464,0 54 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2474,0 55 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2839,0 56 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2469,0 57 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2504,0 58 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2509,0 59 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2846,0 60 0
DESIGN ahb@gpio
VIEW symbol.sb
GRAPHIC 2651,0 61 0
LIBRARY AhbLiteComponents_test
DESIGN ahb@gpio_tester
VIEW test
GRAPHIC 12657,0 64 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 14,0 65 1
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12589,0 70 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12581,0 71 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12573,0 72 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12629,0 73 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12565,0 74 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12557,0 75 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12597,0 76 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12613,0 77 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12621,0 78 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12605,0 79 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13236,0 80 0
LIBRARY AhbLiteComponents_test
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 83
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13194,0 86 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12657,0 87 0
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 90
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13204,0 93 0
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 106
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 107
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13194,0 109 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13201,0 110 1
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12629,0 114 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12565,0 115 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12557,0 116 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12597,0 117 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12613,0 118 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12621,0 119 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12605,0 120 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13228,0 121 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12589,0 122 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12581,0 123 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12573,0 124 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13212,0 125 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 13220,0 126 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12657,0 128 0
DESIGN ahb@gpio_tb
VIEW struct.bd
GRAPHIC 12664,0 129 1
DESIGN ahb@gpio_tb
VIEW struct.bd
NO_GRAPHIC 147

48
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tester_entity.xrf
View File

@@ -1,48 +0,0 @@
DESIGN ahb@gpio_tester
VIEW interface
NO_GRAPHIC 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 50,0 8 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 13,0 15 1
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 668,0 20 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 673,0 21 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 683,0 22 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 658,0 23 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 663,0 24 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 678,0 25 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 688,0 26 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 693,0 27 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 698,0 28 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 703,0 29 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 708,0 30 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 1,0 33 0
DESIGN ahb@gpio_tester
VIEW interface
GRAPHIC 1,0 34 0

12
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tb_entity.xrf
View File

@@ -1,12 +0,0 @@
DESIGN ahb@uart_tb
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN ahb@uart_tb
VIEW symbol.sb
GRAPHIC 53,0 8 0
DESIGN ahb@uart_tb
VIEW symbol.sb
GRAPHIC 1,0 11 0
DESIGN ahb@uart_tb
VIEW symbol.sb
GRAPHIC 1,0 12 0

213
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tb_struct.xrf
View File

@@ -1,213 +0,0 @@
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 187,0 9 0
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 14
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 0,0 18 2
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 1,0 21 0
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 21
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13297,0 28 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13305,0 29 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12627,0 30 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12563,0 31 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12587,0 32 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12579,0 33 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12555,0 34 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12571,0 35 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12595,0 36 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12611,0 37 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12619,0 38 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12603,0 39 0
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 40
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 41
LIBRARY AhbLiteComponents
DESIGN ahb@uart
VIEW student@version
GRAPHIC 13707,0 43 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 14,0 44 1
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2839,0 49 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2452,0 50 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2514,0 51 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2519,0 52 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2692,0 53 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2494,0 54 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2464,0 55 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2474,0 56 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2651,0 57 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2469,0 58 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2504,0 59 0
DESIGN ahb@uart
VIEW symbol.sb
GRAPHIC 2509,0 60 0
LIBRARY AhbLiteComponents_test
DESIGN ahb@uart_tester
VIEW test
GRAPHIC 12657,0 63 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 14,0 64 1
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13307,0 68 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12589,0 69 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12581,0 70 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12573,0 71 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13299,0 72 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12629,0 73 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12565,0 74 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12557,0 75 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12597,0 76 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12613,0 77 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12621,0 78 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12605,0 79 0
LIBRARY AhbLiteComponents_test
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 82
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13707,0 85 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12657,0 86 0
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 89
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 91
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13707,0 93 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13714,0 94 1
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13299,0 99 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12629,0 100 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12565,0 101 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12557,0 102 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12597,0 103 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12613,0 104 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12621,0 105 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12605,0 106 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 13307,0 107 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12589,0 108 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12581,0 109 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12573,0 110 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12657,0 112 0
DESIGN ahb@uart_tb
VIEW struct.bd
GRAPHIC 12664,0 113 1
DESIGN ahb@uart_tb
VIEW struct.bd
NO_GRAPHIC 131

51
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tester_entity.xrf
View File

@@ -1,51 +0,0 @@
DESIGN ahb@uart_tester
VIEW interface
NO_GRAPHIC 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 50,0 8 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 13,0 15 1
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1269,0 19 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1224,0 20 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1229,0 21 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1239,0 22 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1264,0 23 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1214,0 24 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1219,0 25 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1234,0 26 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1244,0 27 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1249,0 28 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1254,0 29 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1259,0 30 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1,0 33 0
DESIGN ahb@uart_tester
VIEW interface
GRAPHIC 1,0 34 0

88
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd
View File

@@ -74,23 +74,23 @@ value " "
) )
(vvPair (vvPair
variable "HDLDir" variable "HDLDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
) )
(vvPair (vvPair
variable "HDSDir" variable "HDSDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
) )
(vvPair (vvPair
variable "SideDataDesignDir" variable "SideDataDesignDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info"
) )
(vvPair (vvPair
variable "SideDataUserDir" variable "SideDataUserDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user"
) )
(vvPair (vvPair
variable "SourceDir" variable "SourceDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
) )
(vvPair (vvPair
variable "appl" variable "appl"
@@ -114,15 +114,15 @@ value "%(unit)_%(view)_config"
) )
(vvPair (vvPair
variable "d" variable "d"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb"
) )
(vvPair (vvPair
variable "d_logical" variable "d_logical"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb"
) )
(vvPair (vvPair
variable "date" variable "date"
value "19.04.2024" value "28.04.2023"
) )
(vvPair (vvPair
variable "day" variable "day"
@@ -134,7 +134,7 @@ value "vendredi"
) )
(vvPair (vvPair
variable "dd" variable "dd"
value "19" value "28"
) )
(vvPair (vvPair
variable "designName" variable "designName"
@@ -162,11 +162,11 @@ value "struct"
) )
(vvPair (vvPair
variable "graphical_source_author" variable "graphical_source_author"
value "remi.heredero" value "axel.amand"
) )
(vvPair (vvPair
variable "graphical_source_date" variable "graphical_source_date"
value "19.04.2024" value "28.04.2023"
) )
(vvPair (vvPair
variable "graphical_source_group" variable "graphical_source_group"
@@ -174,11 +174,11 @@ value "UNKNOWN"
) )
(vvPair (vvPair
variable "graphical_source_host" variable "graphical_source_host"
value "WE2330808" value "WE7860"
) )
(vvPair (vvPair
variable "graphical_source_time" variable "graphical_source_time"
value "14:16:25" value "15:06:49"
) )
(vvPair (vvPair
variable "group" variable "group"
@@ -186,7 +186,7 @@ value "UNKNOWN"
) )
(vvPair (vvPair
variable "host" variable "host"
value "WE2330808" value "WE7860"
) )
(vvPair (vvPair
variable "language" variable "language"
@@ -222,11 +222,11 @@ value "avril"
) )
(vvPair (vvPair
variable "p" variable "p"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd"
) )
(vvPair (vvPair
variable "p_logical" variable "p_logical"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd" value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd"
) )
(vvPair (vvPair
variable "package_name" variable "package_name"
@@ -306,7 +306,7 @@ value "struct"
) )
(vvPair (vvPair
variable "time" variable "time"
value "14:16:25" value "15:06:49"
) )
(vvPair (vvPair
variable "unit" variable "unit"
@@ -314,7 +314,7 @@ value "ahbGpio_tb"
) )
(vvPair (vvPair
variable "user" variable "user"
value "remi.heredero" value "axel.amand"
) )
(vvPair (vvPair
variable "version" variable "version"
@@ -326,11 +326,11 @@ value "struct"
) )
(vvPair (vvPair
variable "year" variable "year"
value "2024" value "2023"
) )
(vvPair (vvPair
variable "yy" variable "yy"
value "24" value "23"
) )
] ]
) )
@@ -668,7 +668,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hReset_n : std_uLogic" st "SIGNAL hReset_n : std_uLogic
"
) )
) )
*13 (Net *13 (Net
@@ -686,7 +687,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hClk : std_uLogic" st "SIGNAL hClk : std_uLogic
"
) )
) )
*14 (Net *14 (Net
@@ -704,7 +706,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hResp : std_uLogic" st "SIGNAL hResp : std_uLogic
"
) )
) )
*15 (Net *15 (Net
@@ -722,7 +725,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hReady : std_uLogic" st "SIGNAL hReady : std_uLogic
"
) )
) )
*16 (Net *16 (Net
@@ -741,7 +745,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,32000,1200" xt "0,0,32000,1200"
st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)
"
) )
) )
*17 (Net *17 (Net
@@ -759,7 +764,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hSel : std_uLogic" st "SIGNAL hSel : std_uLogic
"
) )
) )
*18 (Net *18 (Net
@@ -777,7 +783,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hWrite : std_uLogic" st "SIGNAL hWrite : std_uLogic
"
) )
) )
*19 (Net *19 (Net
@@ -796,7 +803,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,32500,1200" xt "0,0,32500,1200"
st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)" st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)
"
) )
) )
*20 (Net *20 (Net
@@ -815,7 +823,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,32000,1200" xt "0,0,32000,1200"
st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)
"
) )
) )
*21 (Net *21 (Net
@@ -834,7 +843,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,30000,1200" xt "0,0,30000,1200"
st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 )" st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 )
"
) )
) )
*22 (Blk *22 (Blk
@@ -1606,7 +1616,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,28000,1200" xt "0,0,28000,1200"
st "SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0)" st "SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
) )
) )
*48 (Net *48 (Net
@@ -1625,7 +1636,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,28000,1200" xt "0,0,28000,1200"
st "SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0)" st "SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
) )
) )
*49 (Net *49 (Net
@@ -1644,7 +1656,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,28000,1200" xt "0,0,28000,1200"
st "SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0)" st "SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
) )
) )
*50 (Net *50 (Net
@@ -1663,7 +1676,8 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,27500,1200" xt "0,0,27500,1200"
st "SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0)" st "SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0)
"
) )
) )
*51 (Wire *51 (Wire
@@ -2337,8 +2351,8 @@ tm "BdCompilerDirectivesTextMgr"
] ]
associable 1 associable 1
) )
windowSize "164,195,1039,926" windowSize "-8,-8,1928,1048"
viewArea "49240,25632,103588,71748" viewArea "27426,17402,170102,94921"
cachedDiagramExtent "0,0,138000,93000" cachedDiagramExtent "0,0,138000,93000"
pageSetupInfo (PageSetupInfo pageSetupInfo (PageSetupInfo
ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool," ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
@@ -2362,7 +2376,7 @@ boundaryWidth 0
) )
hasePageBreakOrigin 1 hasePageBreakOrigin 1
pageBreakOrigin "29000,19000" pageBreakOrigin "29000,19000"
lastUid 13575,0 lastUid 13522,0
defaultCommentText (CommentText defaultCommentText (CommentText
shape (Rectangle shape (Rectangle
layer 0 layer 0

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55
06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/hds_team_prefs.bak
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@@ -1,55 +0,0 @@
version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
]
syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
VMCurrentDesignHierarchy 0
VMMultipleRepositoryMode 0
VMSnapshotViewMode 0
backupNameClashes 1
clearCaseMaster 0
)
(CustomizeTeamPreferences
version "1.1"
FileTypes [
]
)
]

456
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs
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@@ -1280,7 +1280,6 @@ projectPaths [
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
"C:\\work\\edu\\sem\\labo\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\work\\edu\\sem\\labo\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
"C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
] ]
libMappingsRootDir "" libMappingsRootDir ""
teamLibMappingsRootDir "" teamLibMappingsRootDir ""
@@ -1301,144 +1300,288 @@ exportedDirectories [
exportStdIncludeRefs 1 exportStdIncludeRefs 1
exportStdPackageRefs 1 exportStdPackageRefs 1
) )
printerName "\\\\vmenpprint1\\VS-ENP.23.N308-PRN" printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN"
pageSizes [ pageSizes [
(PageSizeInfo (PageSizeInfo
name "Letter" name "12\" x 18\""
width 783 type 512
height 1013 width 1106
height 1658
) )
(PageSizeInfo (PageSizeInfo
name "Legal" name "11\" x 17\""
type 5
width 783
height 1290
)
(PageSizeInfo
name "Statement"
type 6
width 506
height 783
)
(PageSizeInfo
name "Executive"
type 7
width 667
height 967
)
(PageSizeInfo
name "A3"
type 8
width 1077
height 1523
)
(PageSizeInfo
name "A4"
type 9
width 761
height 1077
)
(PageSizeInfo
name "A5"
type 11
width 536
height 761
)
(PageSizeInfo
name "B4 (JIS)"
type 12
width 932
height 1320
)
(PageSizeInfo
name "B5 (JIS)"
type 13
width 660
height 932
)
(PageSizeInfo
name "11<31>17"
type 17 type 17
width 1013 width 1013
height 1566 height 1566
) )
(PageSizeInfo (PageSizeInfo
name "Envelope #10" name "Legal (8,5\" x 14\")"
type 5
width 783
height 1290
)
(PageSizeInfo
name "Letter (8,5\" x 11\")"
width 783
height 1013
)
(PageSizeInfo
name "Executive (7,25\"x10,5\")"
type 7
width 667
height 967
)
(PageSizeInfo
name "5,5\" x 8,5\""
type 6
width 506
height 783
)
(PageSizeInfo
name "A3 (297 x 420 mm)"
type 8
width 1077
height 1523
)
(PageSizeInfo
name "A4 (210 x 297 mm)"
type 9
width 761
height 1077
)
(PageSizeInfo
name "A5 (148 x 210 mm)"
type 11
width 538
height 761
)
(PageSizeInfo
name "A6 (105 x 148 mm)"
type 70
width 380
height 538
)
(PageSizeInfo
name "B4 JIS (257 x 364 mm)"
type 12
width 932
height 1320
)
(PageSizeInfo
name "B5 JIS (182 x 257 mm)"
type 13
width 660
height 932
)
(PageSizeInfo
name "B6 JIS (128 x 182 mm)"
type 88
width 464
height 660
)
(PageSizeInfo
name "8\" x 13\""
type 518
width 737
height 1198
)
(PageSizeInfo
name "8,25\" x 13\""
type 519
width 760
height 1198
)
(PageSizeInfo
name "8,5\" x 13\""
type 14
width 783
height 1198
)
(PageSizeInfo
name "8.5\" x 13.4\""
type 551
width 783
height 1235
)
(PageSizeInfo
name "Com10 Env.(4,125\"x9,5\")"
type 20 type 20
width 379 width 380
height 875 height 875
) )
(PageSizeInfo (PageSizeInfo
name "Envelope DL" name "Env.Monar.(3,875\"x7,5\")"
type 27
width 399
height 798
)
(PageSizeInfo
name "Envelope C5"
type 28
width 587
height 830
)
(PageSizeInfo
name "Envelope B5"
type 34
width 638
height 907
)
(PageSizeInfo
name "Envelope Monarch"
type 37 type 37
width 357 width 357
height 691 height 691
) )
(PageSizeInfo (PageSizeInfo
name "Japanese Postcard" name "Env. DL (110 x 220 mm)"
type 43 type 27
width 362 width 399
height 536 height 798
) )
(PageSizeInfo (PageSizeInfo
name "A6" name "Env. C6 (114 x 162 mm)"
type 70 type 31
width 380 width 413
height 536 height 587
) )
(PageSizeInfo (PageSizeInfo
name "Double Japan Postcard Rotated" name "Env. C5 (162 x 229 mm)"
type 82 type 28
width 536 width 587
height 725 height 830
) )
(PageSizeInfo (PageSizeInfo
name "Executive (JIS)" name "8K (267 x 390 mm)"
type 119 type 520
width 783 width 968
height 1196 height 1415
) )
(PageSizeInfo (PageSizeInfo
name "Oficio 8.5x13" name "16K (195 x 267 mm)"
type 120 type 521
width 783 width 707
height 1198 height 968
) )
(PageSizeInfo (PageSizeInfo
name "12x18" name "8,25\" x 14\""
type 121 type 522
width 1105 width 760
height 1290
)
(PageSizeInfo
name "11\" x 14\""
type 524
width 1013
height 1290
)
(PageSizeInfo
name "13\" x 19,2\""
type 525
width 1198
height 1769
)
(PageSizeInfo
name "13\" x 19\""
type 526
width 1198
height 1751
)
(PageSizeInfo
name "12,6\" x 19,2\""
type 527
width 1161
height 1769
)
(PageSizeInfo
name "12,6\" x 18,5\""
type 528
width 1161
height 1704
)
(PageSizeInfo
name "13\" x 18\""
type 529
width 1198
height 1658 height 1658
) )
(PageSizeInfo (PageSizeInfo
name "8K 273x394 mm" name "10\" x 14\""
type 139 type 16
width 990 width 921
height 1428 height 1290
) )
(PageSizeInfo (PageSizeInfo
name "16K 197x273 mm" name "10\" x 15\""
type 140 type 546
width 714 width 921
height 990 height 1382
)
(PageSizeInfo
name "11\" x 15\""
type 539
width 1013
height 1382
)
(PageSizeInfo
name "SRA3 (320 x 450 mm)"
type 530
width 1161
height 1632
)
(PageSizeInfo
name "SRA4 (225 x 320 mm)"
type 531
width 816
height 1161
)
(PageSizeInfo
name "Format papier personnalis<69>"
type 256
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size1(215,9 x 279,4 mm)"
type 257
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size2(215,9 x 279,4 mm)"
type 258
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size3(215,9 x 279,4 mm)"
type 259
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size4(215,9 x 279,4 mm)"
type 260
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size5(215,9 x 279,4 mm)"
type 261
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size6(215,9 x 279,4 mm)"
type 262
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size7(215,9 x 279,4 mm)"
type 263
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size8(215,9 x 279,4 mm)"
type 264
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size9(215,9 x 279,4 mm)"
type 265
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size10(215,9 x 279,4 mm)"
type 266
width 783
height 1013
) )
] ]
exportPageSetupInfo (PageSetupInfo exportPageSetupInfo (PageSetupInfo
@@ -4149,7 +4292,7 @@ hdsWorkspaceLocation ""
relativeLibraryRootDir "" relativeLibraryRootDir ""
vmLabelLatestDontAskAgain 0 vmLabelLatestDontAskAgain 0
vmLabelWorkspaceDontAskAgain 0 vmLabelWorkspaceDontAskAgain 0
logWindowGeometry "636x514+308+98" logWindowGeometry "636x406+-823+276"
diagramBrowserTabNo 0 diagramBrowserTabNo 0
showInsertPortHint 0 showInsertPortHint 0
showContentFirstTime 0 showContentFirstTime 0
@@ -6031,96 +6174,6 @@ disableFilters 1
] ]
layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))"
) )
(Viewpoint_v2
name "Parse Errors Report"
TreeListVPDatas [
(TreeListVPData
theList "Hierarchy"
columns [
(TreeListVPData_Column
name "Design Unit Name"
displayName ""
width 150
)
(TreeListVPData_Column
name "Extends"
displayName ""
width 100
)
(TreeListVPData_Column
name "Name"
displayName ""
width 250
)
(TreeListVPData_Column
name "Library"
displayName ""
width 120
)
]
filterString ""
accessRights 2
)
]
SmartTableVPDatas [
(SmartTableVPData
theList "Logical Objects"
columns [
(SmartTableVPData_Column
name "Parse Error"
width 22
alignment 0
)
(SmartTableVPData_Column
name "File Name"
width 150
alignment 0
)
(SmartTableVPData_Column
name "Language"
width 100
alignment 0
)
(SmartTableVPData_Column
name "Library"
width 120
alignment 0
)
(SmartTableVPData_Column
name "Location"
width 200
alignment 0
)
(SmartTableVPData_Column
name "Absolute Path"
width 14
alignment 1
)
]
filterNames [
"Architectures and Modules"
"Configurations"
"Entities"
"Files"
"Instances"
"Packages"
"SV Classes"
"SV Interfaces"
"SV Packages"
"SV Program Blocks"
]
filterString "1"
filterColumn "Parse Error"
matchCase 0
matchWholeWordOnly 0
regularExpression 1
groupNames [
]
disableFilters 1
)
]
layoutExpression "V(A(C(LogicalObjects)))"
)
] ]
WorkTabs [ WorkTabs [
(WorkTab (WorkTab
@@ -6316,7 +6369,6 @@ activeViewpointIdx 0
) )
] ]
ViewpointsOnOutlookBar [ ViewpointsOnOutlookBar [
"Parse Errors Report"
] ]
lastActiveViewpoint "Default Viewpoint" lastActiveViewpoint "Default Viewpoint"
expandedTemplateNodes [ expandedTemplateNodes [
@@ -6332,11 +6384,11 @@ size 180
] ]
displayHierarchy 0 displayHierarchy 0
xPos 0 xPos 0
yPos 9 yPos 0
width 974 width 1936
height 1047 height 1056
activeSidePanelTab 2 activeSidePanelTab 2
activeLibraryTab 5 activeLibraryTab 1
sidePanelSize 278 sidePanelSize 278
showUnixHiddenFiles 0 showUnixHiddenFiles 0
componentBrowserXpos 569 componentBrowserXpos 569

6814
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06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk
View File

@@ -46,7 +46,7 @@ settingsMap [
"GlitchGeneration" "GlitchGeneration"
"1" "1"
"InitCmd" "InitCmd"
"C:/Users/remi.heredero/GIT/2024-sem-labs-herederoremi/06-07-08-09-SystemOnChip/Simulation/ahbUart.do" "$SIMULATION_DIR/beamerSoc.do"
"LogFile" "LogFile"
"" ""
"RemoteHost" "RemoteHost"

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BIN
Libs/Lattice/hds/.cache.dat
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Libs/NanoBlaze/hds/.cache.dat
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