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28
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/README.md
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28
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/README.md
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# NEORV32 Port for running the RISC-V Architecture Tests
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The following tasks are executed by the device makefiles:
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* replace the original processor's IMEM rtl file by a simulation-optimized IMEM (ROM!)
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* `sed` command is used to modify the default testbench (`neorv32/sim/neorv32_tb.simple.vhd`):
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* enable/disable the required `CPU_EXTENSION_RISCV_xxx` VHDL configuration generics in the testbench (`neorv32/sim/neorv32_tb.simple.vhd`)
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* set the processor memory configuration
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* compile test code and install application image to processor's `rtl/core` folder
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* compilation uses the `link.imem_rom.ld` linker script as default; code (the test code) is executed from simulation-optimized IMEM (which is read-only); data including signature is stored to DMEM
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* certain areas in the DMEM are initialized using port code in `model_test.h` (`RVTEST` = 0xbabecafe and `SIGNATURE` = 0xdeadbeef); can be disabled using `RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT`
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* the processor is simulated using the default testbench
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* the results are dumped via the SIM_MODE feature of UART0
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* the according code can be found in the `RVMODEL_HALT` macro in `model_test.h`
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* data output (the "signature") is zero-padded to be always a multiple of 16 bytes
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**Notes**
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:warning: The `Zifencei` test requires the r/w/e capabilities of the original IMEM rtl file.
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Hence, the original file is restored for this test. Also, this test uses `link.imem_ram.ld` as linker script since the
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IMEM is used as RAM to allow self-modifying code.
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:information_source: The `RVMODEL_BOOT` macro in `model_test.h` provides a simple "dummy trap handler" that just advances
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to the next instruction. This trap handler is required for some `C` tests as the NEORV32 will raise an illegal instruction
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exception for **all** unimplemented instructions. The trap handler can be overriden (by changing `mtval` CSR) if a test
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uses the defualt trap handler of the test framework.
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@@ -0,0 +1,6 @@
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NEORV32_MARCH ?= rv32ec
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NEORV32_MABI ?= ilp32e
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NEORV32_CPU_EXTENSION_RISCV_C ?= true
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NEORV32_CPU_EXTENSION_RISCV_E ?= true
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include $(NEORV32_ROOT)/sw/isa-test/common.mk
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@@ -0,0 +1,5 @@
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NEORV32_MARCH ?= rv32e
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NEORV32_MABI ?= ilp32e
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NEORV32_CPU_EXTENSION_RISCV_E ?= true
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include $(NEORV32_ROOT)/sw/isa-test/common.mk
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@@ -0,0 +1,6 @@
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NEORV32_MARCH ?= rv32em
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NEORV32_MABI ?= ilp32e
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NEORV32_CPU_EXTENSION_RISCV_E ?= true
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NEORV32_CPU_EXTENSION_RISCV_M ?= true
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include $(NEORV32_ROOT)/sw/isa-test/common.mk
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@@ -0,0 +1,4 @@
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NEORV32_MARCH ?= rv32ic
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NEORV32_CPU_EXTENSION_RISCV_C ?= true
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include $(NEORV32_ROOT)/sw/isa-test/common.mk
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include $(NEORV32_ROOT)/sw/isa-test/common.mk
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@@ -0,0 +1,4 @@
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NEORV32_MARCH ?= rv32im
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NEORV32_CPU_EXTENSION_RISCV_M ?= true
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include $(NEORV32_ROOT)/sw/isa-test/common.mk
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NEORV32_MARCH ?= rv32im
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NEORV32_LINK ?= link.imem_ram.ld
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NEORV32_MEM_INT_IMEM_SIZE ?= '16384'
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NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI ?= true
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include $(NEORV32_ROOT)/sw/isa-test/common.mk
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NEORV32_CPU_EXTENSION_RISCV_C ?= true
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include $(NEORV32_ROOT)/sw/isa-test/common.mk
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22
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_ram.ld
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Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_ram.ld
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OUTPUT_ARCH( "riscv" )
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ENTRY(rvtest_entry_point)
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SECTIONS
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{
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. = 0x00000000;
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.text :
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{
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*(.text.init)
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. = ALIGN(0x1000);
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*(.text)
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. = ALIGN(0x1000);
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*(.tohost)
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*(.data)
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*(.data.string)
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*(.bss)
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. = ALIGN(0x1000);
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_end = .;
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}
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}
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26
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_rom.ld
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Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_rom.ld
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OUTPUT_ARCH( "riscv" )
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ENTRY(rvtest_entry_point)
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SECTIONS
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{
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. = 0x00000000;
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.text :
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{
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*(.text.init)
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. = ALIGN(0x1000);
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*(.text)
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. = ALIGN(0x1000);
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_end = .;
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}
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. = 0x80000000;
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.data :
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{
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. = ALIGN(0x1000);
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*(.tohost)
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*(.data)
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*(.data.string)
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*(.bss)
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}
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}
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212
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/model_test.h
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Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/model_test.h
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// SPDX-License-Identifier: BSD-3-Clause
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// Modified by Stephan Nolting for the NEORV32 Processor
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#ifndef _COMPLIANCE_MODEL_H
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#define _COMPLIANCE_MODEL_H
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#define RVMODEL_DATA_SECTION \
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.pushsection .tohost,"aw",@progbits; \
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.align 8; .global tohost; tohost: .dword 0; \
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.align 8; .global fromhost; fromhost: .dword 0; \
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.popsection; \
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.align 8; .global begin_regstate; begin_regstate: \
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.word 128; \
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.align 8; .global end_regstate; end_regstate: \
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.word 4;
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//RV_COMPLIANCE_HALT
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// neorv32: this will dump the results via the UART0_SIM_MODE data file output
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// neorv32: due to the modifications on "end_signature" (not 4-aligned) we need to make sure we output a 4-aligned number of data here
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// neorv32: -> for zero-padding of the rest of the SIGNATURE section
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#define RVMODEL_HALT \
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signature_dump: \
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la a0, begin_signature; \
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la a1, end_signature; \
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li a2, 0xFFFFFFA4; \
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signature_dump_loop: \
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beq a0, a1, signature_dump_padding; \
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lw t0, 0(a0); \
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sw t0, 0(a2); \
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addi a0, a0, 4; \
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j signature_dump_loop; \
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nop; \
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nop; \
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signature_dump_padding: \
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andi a0, a1, 0x0000000C; \
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beq a0, zero, signature_dump_end; \
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li t0, 16; \
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sub a0, t0, a0; \
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signature_dump_padding_loop: \
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beq a0, zero, signature_dump_end; \
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sw zero, 0(a2); \
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addi a0, a0, -4; \
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j signature_dump_padding_loop; \
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signature_dump_end: \
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j signature_dump_end
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//TODO: declare the start of your signature region here. Nothing else to be used here.
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// The .align 4 ensures that the signature ends at a 16-byte boundary
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#define RVMODEL_DATA_BEGIN \
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.align 4; .global begin_signature; begin_signature:
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//TODO: declare the end of the signature region here. Add other target specific contents here.
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//neorv32: DO NOT use align_4 here! end_signature is used to indicate the actual "number" of signature words
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#define RVMODEL_DATA_END \
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.global end_signature; end_signature: \
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RVMODEL_DATA_SECTION
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//RVMODEL_BOOT
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// neorv32: enable UART0 (ctrl(28)) and enable UART0_SIM_MODE (ctrl(12))
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// neorv32: initialize the complete RVTEST_DATA section in data RAM (DMEM) with 0xBABECAFE
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// neorv32: initialize the complete SIGNATURE section (that is a multiple of four 32-bit entries) in data RAM (DMEM) with 0xDEADBEEF
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// neorv32: this code also provides a dummy trap handler that just moves on to the next instruction
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// neorv32: -> this trap handler can be overridden by the compliance-suite by modifying mtval
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// neorv32: -> the dummy trap handler is required to deal with the neorv32 X extension (-> all illegal/undefined instruction trigger an exception)
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#ifdef NEORV32_NO_DATA_INIT
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// ------------------------- WITHOUT DATA INIT -------------------------
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#define RVMODEL_BOOT \
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core_init: \
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la x1, core_dummy_trap_handler; \
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csrw mtvec, x1; \
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csrw mie, x0; \
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j uart0_sim_mode_init; \
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nop; \
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nop; \
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.balign 4; \
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core_dummy_trap_handler: \
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csrw mscratch, sp; \
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la sp, end_signature; \
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addi sp, sp, 32; \
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sw x8, 0(sp); \
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sw x9, 4(sp); \
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csrr x8, mcause; \
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blt x8, zero, core_dummy_trap_handler_irq; \
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csrr x8, mepc; \
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core_dummy_trap_handler_exc_c_check: \
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lh x9, 0(x8); \
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andi x9, x9, 3; \
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addi x8, x8, +2; \
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csrw mepc, x8; \
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addi x8, zero, 3; \
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bne x8, x9, core_dummy_trap_handler_irq; \
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core_dummy_trap_handler_exc_uncrompressed: \
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csrr x8, mepc; \
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addi x8, x8, +2; \
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csrw mepc, x8; \
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core_dummy_trap_handler_irq: \
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lw x9, 0(sp); \
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lw x8, 4(sp); \
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csrr sp, mscratch; \
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mret; \
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nop; \
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nop; \
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uart0_sim_mode_init: \
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li a0, 0xFFFFFFA0; \
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sw zero, 0(a0); \
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li a1, 1 << 28; \
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li a2, 1 << 12; \
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or a1, a1, a2; \
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sw a1, 0(a0);
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#else
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// ------------------------- WITH DATA INIT -------------------------
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#define RVMODEL_BOOT \
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core_init: \
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la x1, core_dummy_trap_handler; \
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csrw mtvec, x1; \
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csrw mie, x0; \
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nop; \
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nop; \
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init_rvtest_data: \
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la a0, rvtest_data_begin; \
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la a1, rvtest_data_end; \
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li a2, 0xBABECAFE; \
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init_rvtest_data_loop: \
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beq a0, a1, init_rvtest_data_loop_end; \
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sw a2, 0(a0); \
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addi a0, a0, 4; \
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j init_rvtest_data_loop; \
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init_rvtest_data_loop_end: \
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nop; \
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nop; \
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init_signature: \
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la a0, begin_signature; \
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la a1, end_signature; \
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li a2, 0xDEADBEEF; \
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init_signature_loop: \
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beq a0, a1, init_signature_loop_end; \
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sw a2, 0(a0); \
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addi a0, a0, 4; \
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j init_signature_loop; \
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init_signature_loop_end: \
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j uart0_sim_mode_init; \
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nop; \
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nop; \
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.balign 4; \
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core_dummy_trap_handler: \
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csrw mscratch, sp; \
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la sp, end_signature; \
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addi sp, sp, 32; \
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sw x8, 0(sp); \
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sw x9, 4(sp); \
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csrr x8, mcause; \
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blt x8, zero, core_dummy_trap_handler_irq; \
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csrr x8, mepc; \
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core_dummy_trap_handler_exc_c_check: \
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lh x9, 0(x8); \
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andi x9, x9, 3; \
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addi x8, x8, +2; \
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csrw mepc, x8; \
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addi x8, zero, 3; \
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bne x8, x9, core_dummy_trap_handler_irq; \
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core_dummy_trap_handler_exc_uncrompressed: \
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csrr x8, mepc; \
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addi x8, x8, +2; \
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csrw mepc, x8; \
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core_dummy_trap_handler_irq: \
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lw x9, 0(sp); \
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lw x8, 4(sp); \
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csrr sp, mscratch; \
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mret; \
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nop; \
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nop; \
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uart0_sim_mode_init: \
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li a0, 0xFFFFFFA0; \
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sw zero, 0(a0); \
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li a1, 1 << 28; \
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li a2, 1 << 12; \
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or a1, a1, a2; \
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sw a1, 0(a0);
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#endif
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//RVTEST_IO_INIT
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#define RVMODEL_IO_INIT
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//RVTEST_IO_WRITE_STR
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#define RVMODEL_IO_WRITE_STR(_R, _STR)
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//RVTEST_IO_CHECK
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#define RVMODEL_IO_CHECK()
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//RVTEST_IO_ASSERT_GPR_EQ
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#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
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//RVTEST_IO_ASSERT_SFPR_EQ
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#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
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//RVTEST_IO_ASSERT_DFPR_EQ
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#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
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// TODO: specify the routine for setting machine software interrupt
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#define RVMODEL_SET_MSW_INT
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// TODO: specify the routine for clearing machine software interrupt
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#define RVMODEL_CLEAR_MSW_INT
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// TODO: specify the routine for clearing machine timer interrupt
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#define RVMODEL_CLEAR_MTIMER_INT
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// TODO: specify the routine for clearing machine external interrupt
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#define RVMODEL_CLEAR_MEXT_INT
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#endif // _COMPLIANCE_MODEL_H
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