Klagarge/SEm-Labos
Archived
1
0
Fork 0
Code Activity

Initial commit

Browse Source
This commit is contained in:
github-classroom[bot]
2024-02-23 13:01:05 +00:00
committed by GitHub
commit d212040c30
1914 changed files with 1290006 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

74
Libs/RiscV/NEORV32/sw/isa-test/common.mk Normal file
View File

@@ -0,0 +1,74 @@
ifndef NEORV32_ROOT
$(error NEORV32_ROOT is undefined)
endif
NEORV32_LOCAL_RTL ?= $(NEORV32_ROOT)/sim/work
TARGET_SIM ?= ghdl
TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
$(error Target simulator executable '$(TARGET_SIM)` not found)
endif
NEORV32_MARCH ?= rv32i
NEORV32_MABI ?= ilp32
RISCV_PREFIX ?= riscv32-unknown-elf-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
RISCV_READELF ?= $(RISCV_PREFIX)readelf
RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=$(NEORV32_MARCH) -mabi=$(NEORV32_MABI)
NEORV32_LINK ?= link.imem_rom.ld
COMPILE_TARGET ?= \
$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
$$(RISCV_TARGET_FLAGS) \
-I$(ROOTDIR)/riscv-test-suite/env/ \
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-T$(TARGETDIR)/$(RISCV_TARGET)/$(NEORV32_LINK) \
$$(<) -o $$@
NEORV32_CPU_EXTENSION_RISCV_C ?= false
NEORV32_CPU_EXTENSION_RISCV_E ?= false
NEORV32_CPU_EXTENSION_RISCV_M ?= false
NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI ?= false
NEORV32_MEM_INT_IMEM_SIZE ?= '2097152'
NEORV32_SOFTWARE_EXAMPLE ?= $(NEORV32_ROOT)/sw/example/blink_led
ifeq ($(NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI), true)
RUN_TARGET ?= \
echo "copying/using SIM-only IMEM (pre-initialized RAM!)"; \
rm -f $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; \
cp -f $(NEORV32_ROOT)/sim/simple/neorv32_imem.iram.simple.vhd $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd;
else
RUN_TARGET ?= \
echo "copying/using SIM-only IMEM (pre-initialized ROM!)"; \
rm -f $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; \
cp -f $(NEORV32_ROOT)/sim/simple/neorv32_imem.simple.vhd $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd;
endif
RUN_TARGET += \
cd $(work_dir_isa); \
echo ">"; \
rm -f $(NEORV32_ROOT)/sim/*.out; \
make -C $(NEORV32_SOFTWARE_EXAMPLE) main.elf; \
cp -f $< $(NEORV32_SOFTWARE_EXAMPLE)/main.elf; \
make -C $(NEORV32_SOFTWARE_EXAMPLE) main.bin install; \
touch $(NEORV32_ROOT)/sim/simple/neorv32.uart0.sim_mode.data.out; \
GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_ROOT)/sim/simple/ghdl.run.sh \
--stop-time=$(SIM_TIME) \
-gCPU_EXTENSION_RISCV_A=false \
-gCPU_EXTENSION_RISCV_C=$(NEORV32_CPU_EXTENSION_RISCV_C) \
-gCPU_EXTENSION_RISCV_E=$(NEORV32_CPU_EXTENSION_RISCV_E) \
-gCPU_EXTENSION_RISCV_M=$(NEORV32_CPU_EXTENSION_RISCV_M) \
-gCPU_EXTENSION_RISCV_U=false \
-gCPU_EXTENSION_RISCV_Zicsr=true \
-gCPU_EXTENSION_RISCV_Zifencei=true \
-gEXT_IMEM_C=false \
-gMEM_INT_IMEM_SIZE=$(NEORV32_MEM_INT_IMEM_SIZE); \
cp $(NEORV32_ROOT)/sim/simple/neorv32.uart0.sim_mode.data.out $(*).signature.output; \
echo "<";

28
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/README.md Normal file
View File

@@ -0,0 +1,28 @@
# NEORV32 Port for running the RISC-V Architecture Tests
The following tasks are executed by the device makefiles:
* replace the original processor's IMEM rtl file by a simulation-optimized IMEM (ROM!)
* `sed` command is used to modify the default testbench (`neorv32/sim/neorv32_tb.simple.vhd`):
* enable/disable the required `CPU_EXTENSION_RISCV_xxx` VHDL configuration generics in the testbench (`neorv32/sim/neorv32_tb.simple.vhd`)
* set the processor memory configuration
* compile test code and install application image to processor's `rtl/core` folder
* compilation uses the `link.imem_rom.ld` linker script as default; code (the test code) is executed from simulation-optimized IMEM (which is read-only); data including signature is stored to DMEM
* certain areas in the DMEM are initialized using port code in `model_test.h` (`RVTEST` = 0xbabecafe and `SIGNATURE` = 0xdeadbeef); can be disabled using `RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT`
* the processor is simulated using the default testbench
* the results are dumped via the SIM_MODE feature of UART0
* the according code can be found in the `RVMODEL_HALT` macro in `model_test.h`
* data output (the "signature") is zero-padded to be always a multiple of 16 bytes
**Notes**
:warning: The `Zifencei` test requires the r/w/e capabilities of the original IMEM rtl file.
Hence, the original file is restored for this test. Also, this test uses `link.imem_ram.ld` as linker script since the
IMEM is used as RAM to allow self-modifying code.
:information_source: The `RVMODEL_BOOT` macro in `model_test.h` provides a simple "dummy trap handler" that just advances
to the next instruction. This trap handler is required for some `C` tests as the NEORV32 will raise an illegal instruction
exception for **all** unimplemented instructions. The trap handler can be overriden (by changing `mtval` CSR) if a test
uses the defualt trap handler of the test framework.

6
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/C/Makefile.include Normal file
View File

@@ -0,0 +1,6 @@
NEORV32_MARCH ?= rv32ec
NEORV32_MABI ?= ilp32e
NEORV32_CPU_EXTENSION_RISCV_C ?= true
NEORV32_CPU_EXTENSION_RISCV_E ?= true
include $(NEORV32_ROOT)/sw/isa-test/common.mk

5
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/E/Makefile.include Normal file
View File

@@ -0,0 +1,5 @@
NEORV32_MARCH ?= rv32e
NEORV32_MABI ?= ilp32e
NEORV32_CPU_EXTENSION_RISCV_E ?= true
include $(NEORV32_ROOT)/sw/isa-test/common.mk

6
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/M/Makefile.include Normal file
View File

@@ -0,0 +1,6 @@
NEORV32_MARCH ?= rv32em
NEORV32_MABI ?= ilp32e
NEORV32_CPU_EXTENSION_RISCV_E ?= true
NEORV32_CPU_EXTENSION_RISCV_M ?= true
include $(NEORV32_ROOT)/sw/isa-test/common.mk

4
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/C/Makefile.include Normal file
View File

@@ -0,0 +1,4 @@
NEORV32_MARCH ?= rv32ic
NEORV32_CPU_EXTENSION_RISCV_C ?= true
include $(NEORV32_ROOT)/sw/isa-test/common.mk

1
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/I/Makefile.include Normal file
View File

@@ -0,0 +1 @@
include $(NEORV32_ROOT)/sw/isa-test/common.mk

4
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/M/Makefile.include Normal file
View File

@@ -0,0 +1,4 @@
NEORV32_MARCH ?= rv32im
NEORV32_CPU_EXTENSION_RISCV_M ?= true
include $(NEORV32_ROOT)/sw/isa-test/common.mk

6
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/Zifencei/Makefile.include Normal file
View File

@@ -0,0 +1,6 @@
NEORV32_MARCH ?= rv32im
NEORV32_LINK ?= link.imem_ram.ld
NEORV32_MEM_INT_IMEM_SIZE ?= '16384'
NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI ?= true
include $(NEORV32_ROOT)/sw/isa-test/common.mk

3
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/privilege/Makefile.include Normal file
View File

@@ -0,0 +1,3 @@
NEORV32_CPU_EXTENSION_RISCV_C ?= true
include $(NEORV32_ROOT)/sw/isa-test/common.mk

22
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_ram.ld Normal file
View File

@@ -0,0 +1,22 @@
OUTPUT_ARCH( "riscv" )
ENTRY(rvtest_entry_point)
SECTIONS
{
. = 0x00000000;
.text :
{
*(.text.init)
. = ALIGN(0x1000);
*(.text)
. = ALIGN(0x1000);
*(.tohost)
*(.data)
*(.data.string)
*(.bss)
. = ALIGN(0x1000);
_end = .;
}
}

26
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_rom.ld Normal file
View File

@@ -0,0 +1,26 @@
OUTPUT_ARCH( "riscv" )
ENTRY(rvtest_entry_point)
SECTIONS
{
. = 0x00000000;
.text :
{
*(.text.init)
. = ALIGN(0x1000);
*(.text)
. = ALIGN(0x1000);
_end = .;
}
. = 0x80000000;
.data :
{
. = ALIGN(0x1000);
*(.tohost)
*(.data)
*(.data.string)
*(.bss)
}
}

212
Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/model_test.h Normal file
View File

@@ -0,0 +1,212 @@
// SPDX-License-Identifier: BSD-3-Clause
// Modified by Stephan Nolting for the NEORV32 Processor
#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H
#define RVMODEL_DATA_SECTION \
.pushsection .tohost,"aw",@progbits; \
.align 8; .global tohost; tohost: .dword 0; \
.align 8; .global fromhost; fromhost: .dword 0; \
.popsection; \
.align 8; .global begin_regstate; begin_regstate: \
.word 128; \
.align 8; .global end_regstate; end_regstate: \
.word 4;
//RV_COMPLIANCE_HALT
// neorv32: this will dump the results via the UART0_SIM_MODE data file output
// neorv32: due to the modifications on "end_signature" (not 4-aligned) we need to make sure we output a 4-aligned number of data here
// neorv32: -> for zero-padding of the rest of the SIGNATURE section
#define RVMODEL_HALT \
signature_dump: \
la a0, begin_signature; \
la a1, end_signature; \
li a2, 0xFFFFFFA4; \
signature_dump_loop: \
beq a0, a1, signature_dump_padding; \
lw t0, 0(a0); \
sw t0, 0(a2); \
addi a0, a0, 4; \
j signature_dump_loop; \
nop; \
nop; \
signature_dump_padding: \
andi a0, a1, 0x0000000C; \
beq a0, zero, signature_dump_end; \
li t0, 16; \
sub a0, t0, a0; \
signature_dump_padding_loop: \
beq a0, zero, signature_dump_end; \
sw zero, 0(a2); \
addi a0, a0, -4; \
j signature_dump_padding_loop; \
signature_dump_end: \
j signature_dump_end
//TODO: declare the start of your signature region here. Nothing else to be used here.
// The .align 4 ensures that the signature ends at a 16-byte boundary
#define RVMODEL_DATA_BEGIN \
.align 4; .global begin_signature; begin_signature:
//TODO: declare the end of the signature region here. Add other target specific contents here.
//neorv32: DO NOT use align_4 here! end_signature is used to indicate the actual "number" of signature words
#define RVMODEL_DATA_END \
.global end_signature; end_signature: \
RVMODEL_DATA_SECTION
//RVMODEL_BOOT
// neorv32: enable UART0 (ctrl(28)) and enable UART0_SIM_MODE (ctrl(12))
// neorv32: initialize the complete RVTEST_DATA section in data RAM (DMEM) with 0xBABECAFE
// neorv32: initialize the complete SIGNATURE section (that is a multiple of four 32-bit entries) in data RAM (DMEM) with 0xDEADBEEF
// neorv32: this code also provides a dummy trap handler that just moves on to the next instruction
// neorv32: -> this trap handler can be overridden by the compliance-suite by modifying mtval
// neorv32: -> the dummy trap handler is required to deal with the neorv32 X extension (-> all illegal/undefined instruction trigger an exception)
#ifdef NEORV32_NO_DATA_INIT
// ------------------------- WITHOUT DATA INIT -------------------------
#define RVMODEL_BOOT \
core_init: \
la x1, core_dummy_trap_handler; \
csrw mtvec, x1; \
csrw mie, x0; \
j uart0_sim_mode_init; \
nop; \
nop; \
.balign 4; \
core_dummy_trap_handler: \
csrw mscratch, sp; \
la sp, end_signature; \
addi sp, sp, 32; \
sw x8, 0(sp); \
sw x9, 4(sp); \
csrr x8, mcause; \
blt x8, zero, core_dummy_trap_handler_irq; \
csrr x8, mepc; \
core_dummy_trap_handler_exc_c_check: \
lh x9, 0(x8); \
andi x9, x9, 3; \
addi x8, x8, +2; \
csrw mepc, x8; \
addi x8, zero, 3; \
bne x8, x9, core_dummy_trap_handler_irq; \
core_dummy_trap_handler_exc_uncrompressed: \
csrr x8, mepc; \
addi x8, x8, +2; \
csrw mepc, x8; \
core_dummy_trap_handler_irq: \
lw x9, 0(sp); \
lw x8, 4(sp); \
csrr sp, mscratch; \
mret; \
nop; \
nop; \
uart0_sim_mode_init: \
li a0, 0xFFFFFFA0; \
sw zero, 0(a0); \
li a1, 1 << 28; \
li a2, 1 << 12; \
or a1, a1, a2; \
sw a1, 0(a0);
#else
// ------------------------- WITH DATA INIT -------------------------
#define RVMODEL_BOOT \
core_init: \
la x1, core_dummy_trap_handler; \
csrw mtvec, x1; \
csrw mie, x0; \
nop; \
nop; \
init_rvtest_data: \
la a0, rvtest_data_begin; \
la a1, rvtest_data_end; \
li a2, 0xBABECAFE; \
init_rvtest_data_loop: \
beq a0, a1, init_rvtest_data_loop_end; \
sw a2, 0(a0); \
addi a0, a0, 4; \
j init_rvtest_data_loop; \
init_rvtest_data_loop_end: \
nop; \
nop; \
init_signature: \
la a0, begin_signature; \
la a1, end_signature; \
li a2, 0xDEADBEEF; \
init_signature_loop: \
beq a0, a1, init_signature_loop_end; \
sw a2, 0(a0); \
addi a0, a0, 4; \
j init_signature_loop; \
init_signature_loop_end: \
j uart0_sim_mode_init; \
nop; \
nop; \
.balign 4; \
core_dummy_trap_handler: \
csrw mscratch, sp; \
la sp, end_signature; \
addi sp, sp, 32; \
sw x8, 0(sp); \
sw x9, 4(sp); \
csrr x8, mcause; \
blt x8, zero, core_dummy_trap_handler_irq; \
csrr x8, mepc; \
core_dummy_trap_handler_exc_c_check: \
lh x9, 0(x8); \
andi x9, x9, 3; \
addi x8, x8, +2; \
csrw mepc, x8; \
addi x8, zero, 3; \
bne x8, x9, core_dummy_trap_handler_irq; \
core_dummy_trap_handler_exc_uncrompressed: \
csrr x8, mepc; \
addi x8, x8, +2; \
csrw mepc, x8; \
core_dummy_trap_handler_irq: \
lw x9, 0(sp); \
lw x8, 4(sp); \
csrr sp, mscratch; \
mret; \
nop; \
nop; \
uart0_sim_mode_init: \
li a0, 0xFFFFFFA0; \
sw zero, 0(a0); \
li a1, 1 << 28; \
li a2, 1 << 12; \
or a1, a1, a2; \
sw a1, 0(a0);
#endif
//RVTEST_IO_INIT
#define RVMODEL_IO_INIT
//RVTEST_IO_WRITE_STR
#define RVMODEL_IO_WRITE_STR(_R, _STR)
//RVTEST_IO_CHECK
#define RVMODEL_IO_CHECK()
//RVTEST_IO_ASSERT_GPR_EQ
#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
//RVTEST_IO_ASSERT_SFPR_EQ
#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
//RVTEST_IO_ASSERT_DFPR_EQ
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
// TODO: specify the routine for setting machine software interrupt
#define RVMODEL_SET_MSW_INT
// TODO: specify the routine for clearing machine software interrupt
#define RVMODEL_CLEAR_MSW_INT
// TODO: specify the routine for clearing machine timer interrupt
#define RVMODEL_CLEAR_MTIMER_INT
// TODO: specify the routine for clearing machine external interrupt
#define RVMODEL_CLEAR_MEXT_INT
#endif // _COMPLIANCE_MODEL_H