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Libs/RiscV/NEORV32/sw/common/crt0.S
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261
Libs/RiscV/NEORV32/sw/common/crt0.S
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/* ################################################################################################# */
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/* # << NEORV32 - crt0.S - Start-Up Code >> # */
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/* # ********************************************************************************************* # */
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/* # BSD 3-Clause License # */
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/* # # */
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/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */
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/* # # */
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/* # Redistribution and use in source and binary forms, with or without modification, are # */
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/* # permitted provided that the following conditions are met: # */
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/* # # */
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/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */
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/* # conditions and the following disclaimer. # */
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/* # # */
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/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */
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/* # conditions and the following disclaimer in the documentation and/or other materials # */
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/* # provided with the distribution. # */
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/* # # */
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/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */
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/* # endorse or promote products derived from this software without specific prior written # */
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/* # permission. # */
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/* # # */
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/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */
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/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */
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/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */
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/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */
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/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
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/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */
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/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */
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/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */
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/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */
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/* # ********************************************************************************************* # */
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/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */
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/* ################################################################################################# */
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.file "crt0.S"
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.section .text.boot
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.balign 4
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.global _start
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_start:
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.cfi_startproc
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.cfi_undefined ra
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// ************************************************************************************************
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// This is the very first instruction that is executed after hardware reset. It ensures that x0 is
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// written at least once - the CPU HW will ensure it is always set to zero on any write access.
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// ************************************************************************************************
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lui zero, 0 // "dummy" instruction that uses no reg-file input operands at all
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// ************************************************************************************************
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// Setup pointers using linker script symbols
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// ************************************************************************************************
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__crt0_pointer_init:
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.option push
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.option norelax
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la sp, __crt0_stack_begin // stack pointer
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la gp, __global_pointer$ // global pointer
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.option pop
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// ************************************************************************************************
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// Setup CPU core CSRs (some of them DO NOT have a dedicated
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// reset and need to be explicitly initialized)
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// ************************************************************************************************
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__crt0_cpu_csr_init:
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la x10, __crt0_dummy_trap_handler // configure early trap handler
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csrw mtvec, x10
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csrw mepc, x10 // just to init mepc
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csrw mstatus, zero // disable global IRQ
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csrw mie, zero // absolutely no interrupts sources, thanks
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csrw mcounteren, zero // no access from less-privileged modes to counter CSRs
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li x11, ~5 // stop all counters except for [m]cycle[h] and [m]instret[h]
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csrw 0x320, x11 // = mcountinhibit (literal address for lagacy toolchain compatibility)
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csrw mcycle, zero // reset cycle counters
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csrw mcycleh, zero
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csrw minstret, zero // reset instruction counters
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csrw minstreth, zero
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// ************************************************************************************************
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// Initialize integer register file (lower half)
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// ************************************************************************************************
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__crt0_reg_file_clear:
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//addi x0, x0, 0 // hardwired to zero
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addi x1, x0, 0
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//addi x2, x0, 0 // stack pointer sp
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//addi x3, x0, 0 // global pointer gp
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addi x4, x0, 0
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addi x5, x0, 0
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addi x6, x0, 0
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addi x7, x0, 0
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//addi x8, x0, 0 // implicitly initialized within crt0
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//addi x9, x0, 0 // implicitly initialized within crt0
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//addi x10, x0, 0 // implicitly initialized within crt0
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//addi x11, x0, 0 // implicitly initialized within crt0
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//addi x12, x0, 0 // implicitly initialized within crt0
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//addi x13, x0, 0 // implicitly initialized within crt0
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addi x14, x0, 0
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addi x15, x0, 0
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// ************************************************************************************************
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// Initialize integer register file (upper half, if no E extension)
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// ************************************************************************************************
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#ifndef __riscv_32e
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// do not do this if compiling bootloader (to save some program space)
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#ifndef make_bootloader
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addi x16, x0, 0
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addi x17, x0, 0
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addi x18, x0, 0
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addi x19, x0, 0
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addi x20, x0, 0
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addi x21, x0, 0
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addi x22, x0, 0
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addi x23, x0, 0
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addi x24, x0, 0
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addi x25, x0, 0
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addi x26, x0, 0
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addi x27, x0, 0
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addi x28, x0, 0
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addi x29, x0, 0
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addi x30, x0, 0
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addi x31, x0, 0
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#endif
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#endif
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// ************************************************************************************************
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// Reset/deactivate IO/peripheral devices
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// Devices, that are not implemented, will cause a store bus access fault
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// which is captured (but actually ignored) by the dummy trap handler.
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// ************************************************************************************************
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__crt0_reset_io:
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la x8, __ctr0_io_space_begin // start of processor-internal IO region
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la x9, __ctr0_io_space_end // end of processor-internal IO region
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__crt0_reset_io_loop:
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sw zero, 0(x8)
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addi x8, x8, 4
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bne x8, x9, __crt0_reset_io_loop
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// ************************************************************************************************
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// Clear .bss section (byte-wise) using linker script symbols
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// ************************************************************************************************
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__crt0_clear_bss:
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la x11, __crt0_bss_start
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la x12, __crt0_bss_end
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__crt0_clear_bss_loop:
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bge x11, x12, __crt0_clear_bss_loop_end
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sb zero, 0(x11)
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addi x11, x11, 1
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j __crt0_clear_bss_loop
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__crt0_clear_bss_loop_end:
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// ************************************************************************************************
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// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols
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// ************************************************************************************************
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__crt0_copy_data:
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la x11, __crt0_copy_data_src_begin // start of data area (copy source)
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la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)
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la x13, __crt0_copy_data_dst_end // last address of destination data area
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__crt0_copy_data_loop:
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bge x12, x13, __crt0_copy_data_loop_end
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lb x14, 0(x11)
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sb x14, 0(x12)
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addi x11, x11, 1
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addi x12, x12, 1
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j __crt0_copy_data_loop
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__crt0_copy_data_loop_end:
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// ************************************************************************************************
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// Setup arguments and call main function
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// ************************************************************************************************
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__crt0_main_entry:
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addi x10, zero, 0 // a0 = argc = 0
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addi x11, zero, 0 // a1 = argv = 0
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jal ra, main // call actual app's main function, this "should" not return
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// ************************************************************************************************
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// call "after main" handler (if there is any) if main really returns
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// ************************************************************************************************
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__crt0_main_aftermath:
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csrw mscratch, a0 // copy main's return code in mscratch for debugger
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#ifndef make_bootloader // after_main handler not supported for bootloader
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.weak __neorv32_crt0_after_main
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la ra, __neorv32_crt0_after_main
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beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified
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jalr ra // execute handler, main's return code in a0
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#endif
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// ************************************************************************************************
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// go to endless sleep mode
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// ************************************************************************************************
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__crt0_main_aftermath_end:
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csrci mstatus, 8 // mstatus: disable global IRQs (mstatus.mie)
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__crt0_main_aftermath_end_loop:
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wfi // try to go to sleep mode
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j __crt0_main_aftermath_end_loop // endless loop
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// ************************************************************************************************
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// dummy trap handler (for exceptions & IRQs during very early boot stage)
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// does nothing but tries to move on to next instruction
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// ************************************************************************************************
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.balign 4
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__crt0_dummy_trap_handler:
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addi sp, sp, -8
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sw x8, 0(sp)
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sw x9, 4(sp)
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csrr x8, mcause
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blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt
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csrr x8, mepc
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__crt0_dummy_trap_handler_exc_c_check: // is compressed instruction?
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lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
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andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
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addi x8, x8, +2 // only this for compressed instructions
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csrw mepc, x8 // set return address when compressed instruction
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addi x8, zero, 3
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bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
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__crt0_dummy_trap_handler_exc_uncrompressed: // is uncompressed instruction!
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csrr x8, mepc
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addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions
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csrw mepc, x8
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__crt0_dummy_trap_handler_irq:
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lw x8, 0(sp)
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lw x9, 4(sp)
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addi sp, sp, +8
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mret
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.cfi_endproc
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.end
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