Initial commit

Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/.gitignore

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+/vivado*
+/.Xil
+/work/*

Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/README.md

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+# NEORV32 Test Setup for the Digilent Arty A7-35 FPGA Board
+
+This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Arty A7-35 board.
+It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
+top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs).
+
+* FPGA Board: :books: [Digilent Arty A7-35 FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)
+* FPGA: Xilinx Artix-7 `XC7A35TICSG324-1L`
+* Toolchain: Xilinx Vivado (tested with Vivado 2019.2)
+
+
+## NEORV32 Configuration
+
+:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
+configuration and entity details and [`arty_a7_35_test_setup.xdc`](https://github.com/stnolting/neorv32/blob/master/boards/arty-a7-35-test-setup/arty_a7_35_test_setup.xdc)
+for the according FPGA pin mapping.
+
+* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors)
+* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
+* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
+* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
+* Clock: 100MHz from on-board oscillator
+* Reset: Via dedicated on-board "RESET" button
+* GPIO output port `gpio_o`
+  * bits 0..3 are connected to the green on-board LEDs (LD4 - LD7); LD4 is the bootloader status LED
+  * bits 4..7 are (not actually used) connected to PMOD `JA` connector pins 1-4
+* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip
+
+

Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc

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+## This file is a general .xdc for the Arty A7-35 Rev. D
+
+## For default neorv32_test_setup.vhd top entity
+
+## Clock signal
+set_property -dict { PACKAGE_PIN E3   IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk_i }];
+
+## LEDs
+set_property -dict { PACKAGE_PIN H5   IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; #IO_L24N_T3_35 Sch=led[4]
+set_property -dict { PACKAGE_PIN J5   IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; #IO_25_35 Sch=led[5]
+set_property -dict { PACKAGE_PIN T9   IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
+set_property -dict { PACKAGE_PIN T10  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
+
+## Pmod Header JA (unused GPIO outputs)
+set_property -dict { PACKAGE_PIN G13  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[4] }]; #IO_0_15 Sch=ja[1]
+set_property -dict { PACKAGE_PIN B11  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; #IO_L4P_T0_15 Sch=ja[2]
+set_property -dict { PACKAGE_PIN A11  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; #IO_L4N_T0_15 Sch=ja[3]
+set_property -dict { PACKAGE_PIN D12  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; #IO_L6P_T0_15 Sch=ja[4]
+
+## USB-UART Interface
+set_property -dict { PACKAGE_PIN D10  IOSTANDARD LVCMOS33 } [get_ports { uart0_txd_o }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
+set_property -dict { PACKAGE_PIN A9   IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd_i }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
+
+## Misc.
+set_property -dict { PACKAGE_PIN C2   IOSTANDARD LVCMOS33 } [get_ports { rstn_i }]; #IO_L16P_T2_35 Sch=ck_rst

Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/create_project.tcl

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+set board "arty-a7-35"
+
+# Create and clear output directory
+set outputdir work
+file mkdir $outputdir
+
+set files [glob -nocomplain "$outputdir/*"]
+if {[llength $files] != 0} {
+    puts "deleting contents of $outputdir"
+    file delete -force {*}[glob -directory $outputdir *]; # clear folder contents
+} else {
+    puts "$outputdir is empty"
+}
+
+switch $board {
+  "arty-a7-35" {
+    set a7part "xc7a35ticsg324-1L"
+    set a7prj ${board}-test-setup
+  }
+}
+
+# Create project
+create_project -part $a7part $a7prj $outputdir
+
+set_property board_part digilentinc.com:${board}:part0:1.0 [current_project]
+set_property target_language VHDL [current_project]
+
+# Define filesets
+
+## Core: NEORV32
+add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd
+set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]]
+set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]]
+
+## Design: processor subsystem template, and (optionally) BoardTop and/or other additional sources
+set fileset_design ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd
+
+## Constraints
+set fileset_constraints [glob ./*.xdc]
+
+## Simulation-only sources
+set fileset_sim [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd]
+
+# Add source files
+
+## Design
+add_files $fileset_design
+
+## Constraints
+add_files -fileset constrs_1 $fileset_constraints
+
+## Simulation-only
+add_files -fileset sim_1 $fileset_sim
+
+# Run synthesis, implementation and bitstream generation
+launch_runs impl_1 -to_step write_bitstream -jobs 4
+wait_on_run impl_1