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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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4
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dmem_ram.vhd"]