Klagarge/SEm-Labos
Archived
1
0
Fork 0
Code Activity

Initial commit

Browse Source
This commit is contained in:
github-classroom[bot]
2024-02-23 13:01:05 +00:00
committed by GitHub
commit d212040c30
1914 changed files with 1290006 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore vendored Normal file
View File

@@ -0,0 +1,5 @@
db
incremental_db
output_files
greybox_tmp
*.qws

60
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/README.md Normal file
View File

@@ -0,0 +1,60 @@
# NEORV32 Test Setup using the NEORV32 with AvalonMM Master Interface wrapper
This setup provides a very simple "demo setup" that uses the NEORV32 with a AvalonMM
Interface wrapper. This makes if possible to connect you own modules using a simple
version of the AvalonMM Master interface.
Note that the AvalonMM Master is a very simple version providing only basic features:
* Single read and write access
* Flow control (variable wait-states)
* 8/16/32 bit data access
* Aligned and unaligned access supported
The AvalonMM Master does **not** support:
* Burst access
* Pipeline transfer
* Pending reads
The design is based on the de0-nano-test-setup, but added a AvalonMM Master wrapper.
The wrapper file can be found here [`AvalonMM wrapper`](../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd).
As a test an "external" DMEM is conneced to the NEORV32 over the AvalonMM Master Interface.
It uses the simplified and simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition)
### NEORV32 Configuration
For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used
with a few exceptions:
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader
* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
* Clock: 50MHz from on-board oscillator
* Reset: via on-board button "KEY0"
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
### FPGA Utilization
```
Total logic elements 3,439 / 22,320 ( 15 % )
Total registers 1674
Total pins 12 / 154 ( 8 % )
Total virtual pins 0
Total memory bits 197,632 / 608,256 ( 32 % )
Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
```
## How To Run
Open the Quartus project file, compile and upload to FPGA.

31
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qpf Normal file
View File

@@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
# Date created = 20:23:30 September 13, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "20:23:30 September 13, 2021"
# Revisions
PROJECT_REVISION = "de0-nano-test-setup"

108
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qsf Normal file
View File

@@ -0,0 +1,108 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
# Date created = 20:23:30 September 13, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# de0-nano-test-setup_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_avalonmm
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_application_image.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bootloader_image.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_boot_rom.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_busswitch.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bus_keeper.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cfs.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_alu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_bus.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_control.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_bitmanip.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_fpu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_muldiv.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_shifter.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_decompressor.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_regfile.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dtm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_fifo.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_gpio.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_icache.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_mtime.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_neoled.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_package.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_pwm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_slink.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_spi.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_sysinfo.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_top.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_trng.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_twi.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_uart.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wdt.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wishbone.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_xirq.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE neorv32_test_setup_avalonmm.vhd
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_R8 -to clk_i
set_location_assignment PIN_L3 -to gpio_o[7]
set_location_assignment PIN_B1 -to gpio_o[6]
set_location_assignment PIN_F3 -to gpio_o[5]
set_location_assignment PIN_D1 -to gpio_o[4]
set_location_assignment PIN_A11 -to gpio_o[3]
set_location_assignment PIN_B13 -to gpio_o[2]
set_location_assignment PIN_A13 -to gpio_o[1]
set_location_assignment PIN_A15 -to gpio_o[0]
set_location_assignment PIN_J15 -to rstn_i
set_location_assignment PIN_C3 -to uart0_txd_o
set_location_assignment PIN_A3 -to uart0_rxd_i
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.qip Normal file
View File

@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dmem_ram.vhd"]

163
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd Normal file
View File

@@ -0,0 +1,163 @@
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dmem_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2019 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and any partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details, at
--https://fpgasoftware.intel.com/eula.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY dmem_ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END dmem_ram;
ARCHITECTURE SYN OF dmem_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2048,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
width_a => 32,
width_byteena_a => 4
)
PORT MAP (
address_a => address,
byteena_a => byteena,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

332
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd Normal file
View File

@@ -0,0 +1,332 @@
-- #################################################################################################
-- # << NEORV32 - Test Setup using the AvalonMM Interface >> #
-- # ********************************************************************************************* #
-- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" #
-- # are trademarks of Intel #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.ALL;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_test_setup_avalonmm is
generic (
-- adapt these for your setup --
CLOCK_FREQUENCY : natural := 50000000; -- clock frequency of clk_i in Hz
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes
);
port (
-- Global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
-- UART0 --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic -- UART0 receive data
);
end entity;
architecture neorv32_test_setup_avalonmm_rtl of neorv32_test_setup_avalonmm is
component neorv32_top_avalonmm is
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
-- Internal Instruction memory (IMEM) --
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
-- Internal Data memory (DMEM) --
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
-- Internal Cache memory (iCACHE) --
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- Stream link interface (SLINK) --
SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
-- Processor peripherals --
IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural := 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
);
port (
-- Global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional)
jtag_tck_i : in std_ulogic := 'U'; -- serial clock
jtag_tdi_i : in std_ulogic := 'U'; -- serial data input
jtag_tdo_o : out std_ulogic; -- serial data output
jtag_tms_i : in std_ulogic := 'U'; -- mode select
-- AvalonMM interface
read_o : out std_logic;
write_o : out std_logic;
waitrequest_i : in std_logic := '0';
byteenable_o : out std_logic_vector(3 downto 0);
address_o : out std_logic_vector(31 downto 0);
writedata_o : out std_logic_vector(31 downto 0);
readdata_i : in std_logic_vector(31 downto 0) := (others => '0');
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
slink_tx_dat_o : out sdata_8x32_t; -- output data
slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data
slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input
slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o : out std_ulogic; -- UART1 send data
uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
neoled_o : out std_ulogic; -- async serial data line
-- System time --
mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels
-- CPU interrupts --
mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
);
end component neorv32_top_avalonmm;
-- Intel/Altera RAM module created by MegaWizard
COMPONENT dmem_ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT dmem_ram;
signal con_gpio_o : std_ulogic_vector(63 downto 0);
signal read_o : std_logic;
signal write_o : std_logic;
signal waitrequest_i : std_logic;
signal byteenable_o : std_logic_vector(3 downto 0);
signal address_o : std_logic_vector(31 downto 0);
signal writedata_o : std_logic_vector(31 downto 0);
signal readdata_i : std_logic_vector(31 downto 0);
signal read_wait_cnt : std_logic_vector(1 downto 0);
begin
-- The Core Of The Problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_top_inst: neorv32_top_avalonmm
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
-- Internal Instruction memory --
MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN => false, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => 0, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)?
)
port map (
-- Global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => con_gpio_o, -- parallel output
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart0_txd_o, -- UART0 send data
uart0_rxd_i => uart0_rxd_i, -- UART0 receive data
-- AvalonMM Interface
read_o => read_o,
write_o => write_o,
waitrequest_i => waitrequest_i,
byteenable_o => byteenable_o,
address_o => address_o,
writedata_o => writedata_o,
readdata_i => readdata_i
);
-- Simple example hooking up RAM module to AvalonMM Interface
-- and using this RAM as DMEM
my_dmem_ram : dmem_ram
port map(
address => address_o(12 downto 2),
byteena => byteenable_o,
clock => clk_i,
data => writedata_o,
wren => write_o,
q => readdata_i);
-- Very simple AvalonMM control signals
-- Write has 0 wait-states
-- Read has 2 wait-states
waitrequest_i <= '1' when (read_o = '1' and read_wait_cnt /= "10") else '0';
process(clk_i, rstn_i)
begin
if rstn_i = '0' then
read_wait_cnt <= "00";
elsif rising_edge(clk_i) then
if read_o = '0' then
read_wait_cnt <= "00";
else
read_wait_cnt <= read_wait_cnt + '1';
end if;
end if;
end process;
-- GPIO output --
gpio_o <= con_gpio_o(7 downto 0);
end architecture;