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This commit is contained in:
github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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75
Libs/RiscV/NEORV32/setups/osflow/devices/ecp5/ecp5_components.vhd Normal file
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library ieee ;
use ieee.std_logic_1164.all;
package components is
-- Yosys wrapper components
component EHXPLLL
generic
(
CLKI_DIV : integer := 1;
CLKFB_DIV : integer := 1;
CLKOP_DIV : integer := 8;
CLKOS_DIV : integer := 8;
CLKOS2_DIV : integer := 8;
CLKOS3_DIV : integer := 8;
CLKOP_ENABLE : string := "ENABLED";
CLKOS_ENABLE : string := "DISABLED";
CLKOS2_ENABLE : string := "DISABLED";
CLKOS3_ENABLE : string := "DISABLED";
CLKOP_CPHASE : integer := 0;
CLKOS_CPHASE : integer := 0;
CLKOS2_CPHASE : integer := 0;
CLKOS3_CPHASE : integer := 0;
CLKOP_FPHASE : integer := 0;
CLKOS_FPHASE : integer := 0;
CLKOS2_FPHASE : integer := 0;
CLKOS3_FPHASE : integer := 0;
FEEDBK_PATH : string := "CLKOP";
CLKOP_TRIM_POL : string := "RISING";
CLKOP_TRIM_DELAY : integer := 0;
CLKOS_TRIM_POL : string := "RISING";
CLKOS_TRIM_DELAY : integer := 0;
OUTDIVIDER_MUXA : string := "DIVA";
OUTDIVIDER_MUXB : string := "DIVB";
OUTDIVIDER_MUXC : string := "DIVC";
OUTDIVIDER_MUXD : string := "DIVD";
PLL_LOCK_MODE : integer := 0;
PLL_LOCK_DELAY : integer := 200;
STDBY_ENABLE : string := "DISABLED";
REFIN_RESET : string := "DISABLED";
SYNC_ENABLE : string := "DISABLED";
INT_LOCK_STICKY : string := "ENABLED";
DPHASE_SOURCE : string := "DISABLED";
PLLRST_ENA : string := "DISABLED";
INTFB_WAKE : string := "DISABLED"
);
port
(
CLKI : IN std_logic := 'X';
CLKFB : IN std_logic := 'X';
RST : IN std_logic := 'X';
STDBY : IN std_logic := 'X';
PLLWAKESYNC : IN std_logic := 'X';
PHASESEL1 : IN std_logic := 'X';
PHASESEL0 : IN std_logic := 'X';
PHASEDIR : IN std_logic := 'X';
PHASESTEP : IN std_logic := 'X';
PHASELOADREG : IN std_logic := 'X';
ENCLKOP : IN std_logic := 'X';
ENCLKOS : IN std_logic := 'X';
ENCLKOS2 : IN std_logic := 'X';
ENCLKOS3 : IN std_logic := 'X';
CLKOP : OUT std_logic := 'X';
CLKOS : OUT std_logic := 'X';
CLKOS2 : OUT std_logic := 'X';
CLKOS3 : OUT std_logic := 'X';
LOCK : OUT std_logic := 'X';
INTLOCK : OUT std_logic := 'X';
REFCLK : OUT std_logic := 'X';
CLKINTFB : OUT std_logic := 'X'
);
end component;
end package;

145
Libs/RiscV/NEORV32/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd Normal file
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-- #################################################################################################
-- # << NEORV32 - Processor-Internal DMEM for Lattice iCE40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
-- # Logical size DMEM_SIZE must be less or equal. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
library iCE40;
use iCE40.components.all;
architecture neorv32_dmem_rtl of neorv32_dmem is
-- advanced configuration --------------------------------------------------------------------------------
constant spram_sleep_mode_en_c : boolean := false; -- put DMEM into sleep mode when idle (for low power)
-- -------------------------------------------------------------------------------------------------------
-- IO space: module base address --
constant hi_abb_c : natural := 31; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
-- local signals --
signal acc_en : std_ulogic;
signal mem_cs : std_ulogic;
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di_lo : std_logic_vector(15 downto 0);
signal spram_di_hi : std_logic_vector(15 downto 0);
signal spram_do_lo : std_logic_vector(15 downto 0);
signal spram_do_hi : std_logic_vector(15 downto 0);
signal spram_be_lo : std_logic_vector(03 downto 0);
signal spram_be_hi : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
signal spram_pwr_n : std_logic;
signal spram_cs : std_logic;
begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based DMEM." severity note;
assert not (DMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: DMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error;
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
mem_cs <= acc_en and (rden_i or wren_i);
-- Memory Access --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
imem_spram_lo_inst : SB_SPRAM256KA
port map (
ADDRESS => spram_addr, -- I
DATAIN => spram_di_lo, -- I
MASKWREN => spram_be_lo, -- I
WREN => spram_we, -- I
CHIPSELECT => spram_cs, -- I
CLOCK => spram_clk, -- I
STANDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
POWEROFF => '1', -- I
DATAOUT => spram_do_lo -- O
);
imem_spram_hi_inst : SB_SPRAM256KA
port map (
ADDRESS => spram_addr, -- I
DATAIN => spram_di_hi, -- I
MASKWREN => spram_be_hi, -- I
WREN => spram_we, -- I
CHIPSELECT => spram_cs, -- I
CLOCK => spram_clk, -- I
STANDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
POWEROFF => '1', -- I
DATAOUT => spram_do_hi -- O
);
-- access logic and signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
spram_cs <= std_logic(mem_cs);
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
buffer_ff: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= mem_cs;
rden <= acc_en and rden_i;
end if;
end process buffer_ff;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neorv32_dmem_rtl;

146
Libs/RiscV/NEORV32/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd Normal file
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-- #################################################################################################
-- # << NEORV32 - Processor-Internal IMEM for Lattice iCE40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
-- # Logical size IMEM_SIZE must be less or equal. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
library iCE40;
use iCE40.components.all;
architecture neorv32_imem_rtl of neorv32_imem is
-- advanced configuration --------------------------------------------------------------------------------
constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power)
-- -------------------------------------------------------------------------------------------------------
-- IO space: module base address --
constant hi_abb_c : natural := 31; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
-- local signals --
signal acc_en : std_ulogic;
signal mem_cs : std_ulogic;
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di_lo : std_logic_vector(15 downto 0);
signal spram_di_hi : std_logic_vector(15 downto 0);
signal spram_do_lo : std_logic_vector(15 downto 0);
signal spram_do_hi : std_logic_vector(15 downto 0);
signal spram_be_lo : std_logic_vector(03 downto 0);
signal spram_be_hi : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
signal spram_pwr_n : std_logic;
signal spram_cs : std_logic;
begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based IMEM." severity note;
assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure;
assert not (IMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: IMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error;
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
mem_cs <= acc_en and (rden_i or wren_i);
-- Memory Access --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
imem_spram_lo_inst : SB_SPRAM256KA
port map (
ADDRESS => spram_addr, -- I
DATAIN => spram_di_lo, -- I
MASKWREN => spram_be_lo, -- I
WREN => spram_we, -- I
CHIPSELECT => spram_cs, -- I
CLOCK => spram_clk, -- I
STANDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
POWEROFF => '1', -- I
DATAOUT => spram_do_lo -- O
);
imem_spram_hi_inst : SB_SPRAM256KA
port map (
ADDRESS => spram_addr, -- I
DATAIN => spram_di_hi, -- I
MASKWREN => spram_be_hi, -- I
WREN => spram_we, -- I
CHIPSELECT => spram_cs, -- I
CLOCK => spram_clk, -- I
STANDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
POWEROFF => '1', -- I
DATAOUT => spram_do_hi -- O
);
-- access logic and signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
spram_cs <= std_logic(mem_cs);
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
buffer_ff: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= mem_cs;
rden <= acc_en and rden_i;
end if;
end process buffer_ff;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neorv32_imem_rtl;

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Libs/RiscV/NEORV32/setups/osflow/devices/ice40/sb_ice40_components.vhd Normal file
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library ieee ;
use ieee.std_logic_1164.all;
package components is
-- Yosys / IceCube wrapper components
component SB_GB
port(
GLOBAL_BUFFER_OUTPUT : out std_logic;
USER_SIGNAL_TO_GLOBAL_BUFFER : in std_logic
);
end component;
component SB_HFOSC
generic (
CLKHF_DIV : string
);
port (
CLKHFPU : in std_logic;
CLKHFEN : in std_logic;
CLKHF : out std_logic
);
end component;
component SB_PLL40_CORE is
generic (
FEEDBACK_PATH : string := "SIMPLE";
DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED";
DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED";
SHIFTREG_DIV_MODE : std_logic := '0';
FDA_FEEDBACK : std_logic_vector(3 downto 0) := x"0";
FDA_RELATIVE : std_logic_vector(3 downto 0) := x"0";
PLLOUT_SELECT : string := "GENCLK";
DIVR : std_logic_vector(3 downto 0) := x"0";
DIVF : std_logic_vector(6 downto 0) := "0000000";
DIVQ : std_logic_vector(2 downto 0) := "000";
FILTER_RANGE : std_logic_vector(2 downto 0) := "000";
ENABLE_ICEGATE : bit := '0';
TEST_MODE : bit := '0';
EXTERNAL_DIVIDE_FACTOR : integer := 1
);
port (
REFERENCECLK : in std_logic;
PLLOUTCORE : out std_logic;
PLLOUTGLOBAL : out std_logic;
EXTFEEDBACK : in std_logic;
DYNAMICDELAY : in std_logic_vector(7 downto 0);
LOCK : out std_logic;
BYPASS : in std_logic;
RESETB : in std_logic;
LATCHINPUTVALUE : in std_logic;
SDO : out std_logic;
SDI : in std_logic;
SCLK : in std_logic
);
end component;
component SB_PLL40_PAD
generic (
FEEDBACK_PATH : string := "SIMPLE";
DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED";
DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED";
SHIFTREG_DIV_MODE : bit_vector(1 downto 0) := "00";
FDA_FEEDBACK : bit_vector(3 downto 0) := "0000";
FDA_RELATIVE : bit_vector(3 downto 0) := "0000";
PLLOUT_SELECT : string := "GENCLK";
DIVR : bit_vector(3 downto 0) := x"0";
DIVF : bit_vector(6 downto 0) := "0000000";
DIVQ : bit_vector(2 downto 0) := "000";
FILTER_RANGE : bit_vector(2 downto 0) := "000";
ENABLE_ICEGATE : bit := '0';
TEST_MODE : bit := '0';
EXTERNAL_DIVIDE_FACTOR : integer := 1
);
port (
PACKAGEPIN : in std_logic;
PLLOUTCORE : out std_logic;
PLLOUTGLOBAL : out std_logic;
EXTFEEDBACK : in std_logic;
DYNAMICDELAY : in std_logic_vector(7 downto 0);
LOCK : out std_logic;
BYPASS : in std_logic;
RESETB : in std_logic;
LATCHINPUTVALUE : in std_logic;
SDO : out std_logic;
SDI : in std_logic;
SCLK : in std_logic
);
end component;
component SB_RGBA_DRV
generic (
CURRENT_MODE : string := "0b0";
RGB0_CURRENT : string := "0b000000";
RGB1_CURRENT : string := "0b000000";
RGB2_CURRENT : string := "0b000000"
);
port (
RGB0PWM : in std_logic;
RGB1PWM : in std_logic;
RGB2PWM : in std_logic;
CURREN : in std_logic;
RGBLEDEN : in std_logic;
RGB0 : out std_logic;
RGB1 : out std_logic;
RGB2 : out std_logic
);
end component;
component SB_SPRAM256KA
port (
ADDRESS : in std_logic_vector(13 downto 0);
DATAIN : in std_logic_vector(15 downto 0);
MASKWREN : in std_logic_vector(3 downto 0);
WREN : in std_logic;
CHIPSELECT : in std_logic;
CLOCK : in std_logic;
STANDBY : in std_logic;
SLEEP : in std_logic;
POWEROFF : in std_logic;
DATAOUT : out std_logic_vector(15 downto 0)
);
end component;
end package;