Initial commit

2024-02-23 13:01:05 +00:00
commit d212040c30
1914 changed files with 1290006 additions and 0 deletions
--- a/Libs/RiscV/HEIRV32/hdl/mux4To1ULogVec_rtl.vhd
+++ b/Libs/RiscV/HEIRV32/hdl/mux4To1ULogVec_rtl.vhd
@@ -0,0 +1,16 @@
+
+ARCHITECTURE rtl OF mux4To1ULogVec IS
+BEGIN
+
+  muxSelect: process(sel, in1, in2, in3, in4)
+  begin
+    case to_integer(unsigned(sel)) is
+      when 0 => out1 <= in1 after g_tMux;
+      when 1 => out1 <= in2 after g_tMux;
+      when 2 => out1 <= in3 after g_tMux;
+      when 3 => out1 <= in4 after g_tMux;
+      when others => out1 <= (others => 'X') after g_tMux;
+    end case;
+  end process muxSelect;
+
+END ARCHITECTURE rtl;