Initial commit

Libs/RiscV/HEIRV32/hdl/bufferStdULogEnable_rtl.vhd

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+
+ARCHITECTURE rtl OF bufferStdULogEnable IS
+BEGIN
+
+    buffering:process(rst, CLK)
+	begin
+		if rst = '1' then
+			out1 <= (others=>'0');
+		elsif rising_edge(CLK) then
+			if EN = '1' then
+				out1 <= in1;
+			end if;
+		end if;
+	end process buffering;
+	
+END ARCHITECTURE rtl;
+