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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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Libs/RiscV/HEIRV32/hdl/bramAddrReducer_rtl.vhd Normal file
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ARCHITECTURE rtl OF bramAddrReducer IS
BEGIN
-- +2 to srr(2) the address (as it makes +4)
addrOut <= std_ulogic_vector(addrIn(addrOut'high+2 downto addrOut'low+2));
END ARCHITECTURE rtl;