Initial commit

Libs/RiscV/HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd

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+
+ARCHITECTURE rtl OF instrDecoder IS
+BEGIN
+
+    decode : process(op)
+    begin
+        case op is
+            when "0000011" => immSrc <= "00"; -- lw
+            when "0100011" => immSrc <= "01"; -- sw
+            when "0110011" => immSrc <= "--"; -- R-type
+            when "1100011" => immSrc <= "10"; -- beq
+            when "0010011" => immSrc <= "00"; -- l-type ALU
+            when "1101111" => immSrc <= "11"; -- jal
+            when others => immSrc <= "--"; -- unknwon
+        end case;
+    end process decode;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/MultiCycle/hdl/instructionForwarder_rtl.vhd

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+
+ARCHITECTURE rtl OF instructionForwarder IS
+    signal lvec_irMem : std_ulogic_vector(readData'range);
+BEGIN
+
+--    forwardIR : process(rst, clk)
+--    begin
+--        if rst = '1' then
+--            lvec_irMem <= (others => '0');
+--        elsif rising_edge(clk) then
+--            if en = '1' and IRWrite = '1' then
+--                lvec_irMem <= readData;
+--            end if;
+--        end if;
+--    end process forwardIR;
+
+    forwardIR : process(readData, irWrite)
+    begin
+        if irWrite = '1' then
+            lvec_irMem <= readData;
+        end if;
+    end process forwardIR;
+
+    instruction <= lvec_irMem;
+
+END ARCHITECTURE rtl;