Initial commit

Libs/RS232/hdl/cmdRs232Mux_RTL.vhd

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+ARCHITECTURE RTL OF rs232Mux IS
+
+  signal passThrough: std_ulogic;
+
+BEGIN
+
+  passThrough <= not selOther;
+
+  multiplexer: process(passThrough, txData, txFullF, TxWr, otherData, otherWr)
+  begin
+    if passThrough = '1' then
+      txDataF <= txData;
+      txWrF <= TxWr;
+      txFull <= txFullF;
+      otherFull <= '1';
+    else
+      txDataF <= otherData;
+      txWrF <= otherWr;
+      otherFull <= txFullF;
+      txFull <= '1';
+    end if;
+  end process multiplexer;
+
+END ARCHITECTURE RTL;

Libs/RS232/hdl/serialPortReceiver_rtl.vhd

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+--===========================================================================--
+--  Design units : CoCa.serialPortReceiver.rtl
+--
+--  File name : serialPortReceiver_rtl.vhd
+--
+--  Purpose : Decode data from UART into words
+--
+--  Input : serial line data
+--
+--  Output : 
+--      dataOut : word of data
+--      dataValid : active when a new word of data is available
+--
+--
+--  Limitations : 
+--  
+--  
+--
+--  Errors: : None known
+--
+--  Library : Common
+--
+--  Dependencies : None
+--
+--  Author : 
+--  Haute école d'ingénierie (HEI/HES-SO)
+--  Institut systèmes industriels (ISI)
+--  Rue de l'industrie 23
+--  1950 Sion
+--  Switzerland (CH)
+--
+--  Simulator : Mentor ModelSim V10.7c
+------------------------------------------------
+--  Revision list
+--  Version Author Date Changes
+--
+--  V1.0 04.04.2022 - First version
+--===========================================================================--
+
+library Common;
+  use Common.CommonLib.all;
+
+architecture RTL of serialPortReceiver is
+
+  signal dividerCounter: unsigned(requiredBitNb(baudRateDivide-1)-1 downto 0);
+  signal dividerCounterReset: std_uLogic;
+  signal rxDelayed: std_uLogic;
+  signal dividerCounterSynchronize: std_uLogic;
+  signal rxSample: std_uLogic;
+  signal rxShiftReg: std_ulogic_vector(dataBitNb-1 downto 0);
+  signal rxReceiving: std_uLogic;
+  signal rxDataValid: std_uLogic;
+  signal rxCounter: unsigned(requiredBitNb(dataBitNb)-1 downto 0);
+
+begin
+
+  divide: process(reset, clock)
+  begin
+    if reset = '1' then
+      dividerCounter <= (others => '0');
+    elsif rising_edge(clock) then
+      if dividerCounterSynchronize = '1' then
+        dividerCounter <= to_unsigned(baudRateDivide/2, dividerCounter'length);
+      elsif dividerCounterReset = '1' then
+        dividerCounter <= (others => '0');
+      else
+        dividerCounter <= dividerCounter + 1;
+      end if;
+    end if;
+  end process divide;
+
+  endOfCount: process(dividerCounter)
+  begin
+    if dividerCounter = baudRateDivide-1 then
+      dividerCounterReset <= '1';
+    else
+      dividerCounterReset <= '0';
+    end if;
+  end process endOfCount;
+
+  delayRx: process(reset, clock)
+  begin
+    if reset = '1' then
+      rxDelayed <= '0';
+    elsif rising_edge(clock) then
+      rxDelayed <= RxD;
+    end if;
+  end process delayRx;
+
+  rxSynchronize: process(RxD, rxDelayed)
+  begin
+    if RxD /= rxDelayed then
+      dividerCounterSynchronize <= '1';
+    else
+      dividerCounterSynchronize <= '0';
+    end if;
+  end process rxSynchronize;
+
+  rxSample <= dividerCounterReset and not dividerCounterSynchronize;
+
+  shiftReg: process(reset, clock)
+  begin
+    if reset = '1' then
+      rxShiftReg <= (others => '0');
+    elsif rising_edge(clock) then
+      if rxSample = '1' then
+        rxShiftReg(rxShiftReg'high-1 downto 0) <= rxShiftReg(rxShiftReg'high downto 1);
+        rxShiftReg(rxShiftReg'high) <= RxD;
+      end if;
+    end if;
+  end process shiftReg;
+
+  detectReceive: process(reset, clock)
+  begin
+    if reset = '1' then
+      rxReceiving <= '0';
+      rxDataValid <= '0';
+    elsif rising_edge(clock) then
+      if rxSample = '1' then
+        if rxCounter = dataBitNb-1 then
+          rxDataValid <= '1';
+        elsif RxD = '0' then
+          rxReceiving <= '1';
+        end if;
+      elsif rxDataValid = '1' then
+        rxReceiving <= '0';
+        rxDataValid <= '0';
+      end if;
+    end if;
+  end process detectReceive;
+
+  countRxBitNb: process(reset, clock)
+  begin
+    if reset = '1' then
+      rxCounter <= (others => '0');
+    elsif rising_edge(clock) then
+      if rxSample = '1' then
+        if rxReceiving = '1' then
+          rxCounter <= rxCounter + 1;
+        else
+          rxCounter <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process countRxBitNb;
+
+  dataOut <= rxShiftReg;
+  dataValid <= rxDataValid;
+
+end RTL;
+

Libs/RS232/hdl/serialPortTransmitter_rtl.vhd

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+--===========================================================================--
+--  Design units : CoCa.serialPortTransmitter.rtl
+--
+--  File name : serialPortTransmitter.vhd
+--
+--  Purpose : Transmit a 8 bit data word over a serial line
+--            add start and stop bits
+--
+--  Parameters : dataBitNb : number of data bits
+--               stopBitNb : number of stop bits
+--
+--  
+--
+--  Errors: : None known
+--
+--  Library : Common
+--
+--  Dependencies : None
+--
+--  Author : 
+--  Haute ecole d'ingenierie (HEI/HES-SO)
+--  Institut systemes industriels (ISI)
+--  Rue de l'industrie 23
+--  1950 Sion
+--  Switzerland (CH)
+--
+--  Simulator : Mentor ModelSim V10.7c
+------------------------------------------------
+--  Revision list
+--  Version Author Date Changes
+--
+--  V1.0 04.04.2022 - First version
+--===========================================================================--
+
+library Common;
+  use Common.CommonLib.all;
+
+architecture RTL of serialPortTransmitter is
+
+  signal dividerCounter: unsigned(requiredBitNb(baudRateDivide)-1 downto 0);
+  signal dividerCounterReset: std_uLogic;
+  signal txData: unsigned(dataBitNb-1 downto 0);
+  signal send1: std_uLogic;
+  signal txShiftEnable: std_uLogic;
+  signal txShiftReg: unsigned(dataBitNb+stopBitNb downto 0);
+  signal txSendingByte: std_uLogic;
+  signal txSendingByteAndStop: std_uLogic;
+
+begin
+
+  divide: process(reset, clock)
+  begin
+    if reset = '1' then
+      dividerCounter <= (others => '0');
+    elsif rising_edge(clock) then
+      if dividerCounterReset = '1' then
+        dividerCounter <= to_unsigned(1, dividerCounter'length);
+      else
+        dividerCounter <= dividerCounter + 1;
+      end if;
+    end if;
+  end process divide;
+
+  endOfCount: process(dividerCounter, send1)
+  begin
+    if dividerCounter = baudRateDivide then
+      dividerCounterReset <= '1';
+    elsif send1 = '1' then
+      dividerCounterReset <= '1';
+    else
+      dividerCounterReset <= '0';
+    end if;
+  end process endOfCount;
+
+  txShiftEnable <= dividerCounterReset;
+
+  storeData: process(reset, clock)
+  begin
+    if reset = '1' then
+      txData <= (others => '1');
+    elsif rising_edge(clock) then
+      if send = '1' then
+        txData <= unsigned(dataIn);
+      end if;
+    end if;
+  end process storeData;
+
+  delaySend: process(reset, clock)
+  begin
+    if reset = '1' then
+      send1 <= '0';
+    elsif rising_edge(clock) then
+      send1 <= send;
+    end if;
+  end process delaySend;
+
+  shiftReg: process(reset, clock)
+  begin
+    if reset = '1' then
+      txShiftReg <= (others => '1');
+    elsif rising_edge(clock) then
+      if txShiftEnable = '1' then
+        if send1 = '1' then
+          txShiftReg <= (others => '1');                 -- stop bits
+          txShiftReg(0) <= '0';                          -- start bit
+          txShiftReg(txData'high+1 downto 1) <= txData;  -- data
+          txShiftReg(txShiftReg'high) <= '0';            -- end flag
+        else
+          txShiftReg <= shift_right(txShiftReg, 1);
+          txShiftReg(txShiftReg'high) <= '1';
+        end if;
+      end if;
+    end if;
+  end process shiftReg;
+
+  txSendingByte <= '1' when
+    (txShiftReg(txShiftReg'high downto 1) /= (txShiftReg'high downto 1 => '1'))
+    else '0';
+
+  txSendingByteAndStop <= '1' when
+    txShiftReg /= (txShiftReg'high downto 0 => '1')
+    else '0';
+
+  TxD <= txShiftReg(0) when txSendingByte = '1' else '1';
+  busy <= txSendingByteAndStop or send1 or send;
+
+end RTL;