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565
Libs/NanoBlaze/hdl/nanoAsm.pl
Normal file
565
Libs/NanoBlaze/hdl/nanoAsm.pl
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@@ -0,0 +1,565 @@
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#!/usr/bin/env perl
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my $indent = ' ' x 2;
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my $separator = '-' x 80;
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################################################################################
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# Input arguments
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#
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use Getopt::Std;
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my %opts;
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getopts('hva:d:r:kz', \%opts);
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die("\n".
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"Usage: $0 [options] fileSpec\n".
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"\n".
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"Options:\n".
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"${indent}-h display this help message\n".
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"${indent}-v verbose\n".
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"${indent}-a bitNb the number of program address bits\n".
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"${indent}-d bitNb the number of data bits\n".
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"${indent}-r bitNb the number of register address bits\n".
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"${indent}-k keep source comments in VHDL code\n".
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"${indent}-z zero don't care bits in VHDL ROM code\n".
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"\n".
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"Assemble code to VHDL for the nanoBlaze processor.\n".
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"\n".
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"More information with: perldoc $0\n".
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"\n".
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""
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) if ($opts{h});
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my $verbose = $opts{v};
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my $keepComments = $opts{k};
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my $zeroDontCares = $opts{z};
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my $addressBitNb = $opts{a} || 10;
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my $registerBitNb = $opts{d} || 8;
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my $registerAddressBitNb = $opts{r} || 4;
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my $asmFileSpec = $ARGV[0] || 'nanoTest.asm';
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my $outFileSpec = $ARGV[1] || 'rom_mapped.vhd';
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#-------------------------------------------------------------------------------
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# System constants
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#
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my $binaryOpCodeLength = 6;
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my $binaryBranchLength = 5;
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my $binaryBranchConditionLength = 3;
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my $opCodeBaseLength = 10;
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my $vhdlAddressLength = 14;
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#-------------------------------------------------------------------------------
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# Derived values
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#
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# file specs
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my $baseFileSpec = $asmFileSpec;
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$baseFileSpec =~ s/\..*//i;
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my $asm1FileSpec = "$baseFileSpec.asm1"; # formatted assembly code
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my $asm2FileSpec = "$baseFileSpec.asm2"; # code with addresses replaced
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my $vhdlFileSpec = "$baseFileSpec.vhd";
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# instruction length
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my $binaryOperationInstructionLength =
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$binaryOpCodeLength +
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$registerAddressBitNb +
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$registerBitNb;
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my $binaryBranchInstructionLength =
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$binaryBranchLength +
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$binaryBranchConditionLength +
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$addressBitNb;
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my $binaryInstructionLength = $binaryOperationInstructionLength;
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if ($binaryBranchInstructionLength > $binaryInstructionLength) {
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$binaryInstructionLength = $binaryBranchInstructionLength
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}
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# assembler string lengths
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my $registerCharNb = int( ($registerBitNb-1)/4 ) + 1;
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my $addressCharNb = int( ($addressBitNb-1)/4 ) + 1;
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# vhdl string lengths
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my $vhdlOpCodeLength = $binaryOpCodeLength + 4;
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my $opCodeTotalLength = 22 + $registerCharNb;
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my $vhdlOperand1Length = $registerAddressBitNb + 3;
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my $vhdlOperand2Length = $registerBitNb + 4;
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if ($addressBitNb + 3 > $vhdlOperand2Length) {
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$vhdlOperand2Length = $addressBitNb + 3
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}
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my $vhdlTotalLength = $vhdlOpCodeLength;
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$vhdlTotalLength = $vhdlTotalLength + $vhdlOperand1Length + $vhdlOperand2Length;
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$vhdlTotalLength = $vhdlTotalLength + 2*2; # '& '
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$vhdlTotalLength = $vhdlTotalLength + 1; # ','
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#-------------------------------------------------------------------------------
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# System variables
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#
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my %constants = ();
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my %addresses = ();
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################################################################################
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# Functions
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#
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#-------------------------------------------------------------------------------
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# Find constant from "CONSTANT" statement
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#
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sub findNewConstant {
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my ($codeLine) = @_;
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$codeLine =~ s/CONSTANT\s+//;
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my ($name, $value) = split(/,\s*/, $codeLine);
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$value = hex($value);
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return ($name, $value);
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}
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#-------------------------------------------------------------------------------
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# Find address from "ADDRESS" statement
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#
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sub findNewAddress {
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my ($codeLine) = @_;
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$codeLine =~ s/ADDRESS\s*//;
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my $address = hex($codeLine);
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return $address;
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}
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#-------------------------------------------------------------------------------
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# Format opcodes
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#
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sub prettyPrint {
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my ($codeLine) = @_;
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my ($opcode, $arguments) = split(/ /, $codeLine, 2);
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$opcode = $opcode . ' ' x ($opCodeBaseLength - length($opcode));
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$arguments =~ s/,*\s+/, /;
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$codeLine = $opcode . $arguments;
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return $codeLine;
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}
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#-------------------------------------------------------------------------------
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# Format to binary
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#
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sub toBinary {
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my ($operand, $bitNb) = @_;
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#$operand = sprintf("%0${bitNb}b", $operand);
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my $hexCharNb = int($bitNb/4) + 1;
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$operand = sprintf("%0${hexCharNb}X", $operand);
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$operand =~ s/0/0000/g;
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$operand =~ s/1/0001/g;
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$operand =~ s/2/0010/g;
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$operand =~ s/3/0011/g;
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$operand =~ s/4/0100/g;
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$operand =~ s/5/0101/g;
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$operand =~ s/6/0110/g;
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$operand =~ s/7/0111/g;
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$operand =~ s/8/1000/g;
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$operand =~ s/9/1001/g;
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$operand =~ s/A/1010/g;
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$operand =~ s/B/1011/g;
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$operand =~ s/C/1100/g;
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$operand =~ s/D/1101/g;
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$operand =~ s/E/1110/g;
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$operand =~ s/F/1111/g;
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$operand = substr($operand, length($operand)-$bitNb, $bitNb);
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return $operand;
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}
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################################################################################
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# Program start
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#
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#-------------------------------------------------------------------------------
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# Display information
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#
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if ($verbose > 0) {
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print "$separator\n";
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print "Assembling $asmFileSpec to $vhdlFileSpec\n";
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}
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#-------------------------------------------------------------------------------
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# Calculate adresses, store address labels
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#
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if ($verbose > 0) {
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print "${indent}Pass 1: from $asmFileSpec to $asm1FileSpec\n";
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}
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my $romAddress = 0;
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open(asmFile, "<$asmFileSpec") or die "Unable to open file, $!";
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open(asm1File, ">$asm1FileSpec") or die "Unable to open file, $!";
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while(my $line = <asmFile>) {
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chomp($line);
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# split code and comment
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my ($codeLine, $comment) = split(/;/, $line, 2);
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# handle address label
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if ($codeLine =~ m/:/) {
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(my $label, $codeLine) = split(/:/, $codeLine);
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$label =~ s/\s*//;
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print asm1File "; _${label}_:\n";
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$addresses{$label} = sprintf("%0${addressCharNb}X", $romAddress);
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}
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# cleanup code
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$codeLine =~ s/\s+/ /g;
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$codeLine =~ s/\A\s//;
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$codeLine =~ s/\s\Z//;
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$codeLine =~ s/\s,/,/;
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if ($codeLine) {
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# handle ADDRESS declaration
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if ($codeLine =~ m/ADDRESS/) {
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$romAddress = findNewAddress($codeLine);
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}
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# handle CONSTANT declaration
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elsif ($codeLine =~ m/CONSTANT/) {
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($name, $value) = findNewConstant($codeLine);
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$constants{$name} = sprintf("%0${registerCharNb}X", $value);
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}
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# print cleaned-up code
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else {
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$codeLine = prettyPrint($codeLine);
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print asm1File sprintf("%0${addressCharNb}X", $romAddress), ": $codeLine";
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if ($comment) {
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print asm1File " ;$comment";
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}
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print asm1File "\n";
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$romAddress = $romAddress + 1;
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}
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}
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else {
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print asm1File ";$comment\n";
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}
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}
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close(asmFile);
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close(asm1File);
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#-------------------------------------------------------------------------------
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# Replace constant values and address labels
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#
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if ($verbose > 0) {
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print "${indent}Pass 2: from $asm1FileSpec to $asm2FileSpec\n";
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}
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open(asm2File, ">$asm2FileSpec") or die "Unable to open file, $!";
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open(asm1File, "<$asm1FileSpec") or die "Unable to open file, $!";
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while(my $line = <asm1File>) {
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chomp($line);
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# split code and comment
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my ($opcode, $comment) = split(/;/, $line, 2);
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if ( ($line =~ m/;/) and ($comment eq '') ) {
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$comment = ' ';
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}
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# cleanup code
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$opcode =~ s/\s+\Z//;
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# replace constants
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foreach my $name (keys %constants) {
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$opcode =~ s/$name/$constants{$name}/g;
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}
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# replace addresses
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foreach my $label (keys %addresses) {
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$opcode =~ s/$label/$addresses{$label}/g;
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}
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# cleanup code
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$opcode = uc($opcode);
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$opcode =~ s/\sS([0-9A-F])/ s$1/g;
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# print cleaned-up code
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if ($comment) {
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if ($opcode) {
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$opcode = $opcode . ' ' x ($opCodeTotalLength - length($opcode));
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}
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$comment =~ s/\s+\Z//;
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print asm2File "$opcode;$comment\n";
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}
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else {
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print asm2File "$opcode\n";
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}
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}
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close(asm1File);
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close(asm2File);
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#-------------------------------------------------------------------------------
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# Write VHDL ROM code
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#
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if ($verbose > 0) {
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print "${indent}Pass 3: from $asm2FileSpec to $vhdlFileSpec\n";
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}
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open(vhdlFile, ">$vhdlFileSpec") or die "Unable to open file, $!";
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print vhdlFile <<DONE;
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ARCHITECTURE mapped OF programRom IS
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subtype opCodeType is std_ulogic_vector(5 downto 0);
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constant opLoadC : opCodeType := "000000";
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constant opLoadR : opCodeType := "000001";
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constant opInputC : opCodeType := "000100";
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constant opInputR : opCodeType := "000101";
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constant opFetchC : opCodeType := "000110";
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constant opFetchR : opCodeType := "000111";
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constant opAndC : opCodeType := "001010";
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constant opAndR : opCodeType := "001011";
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constant opOrC : opCodeType := "001100";
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constant opOrR : opCodeType := "001101";
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constant opXorC : opCodeType := "001110";
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constant opXorR : opCodeType := "001111";
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constant opTestC : opCodeType := "010010";
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constant opTestR : opCodeType := "010011";
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constant opCompC : opCodeType := "010100";
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constant opCompR : opCodeType := "010101";
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constant opAddC : opCodeType := "011000";
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constant opAddR : opCodeType := "011001";
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constant opAddCyC : opCodeType := "011010";
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constant opAddCyR : opCodeType := "011011";
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constant opSubC : opCodeType := "011100";
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constant opSubR : opCodeType := "011101";
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constant opSubCyC : opCodeType := "011110";
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constant opSubCyR : opCodeType := "011111";
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constant opShRot : opCodeType := "100000";
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constant opOutputC : opCodeType := "101100";
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constant opOutputR : opCodeType := "101101";
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constant opStoreC : opCodeType := "101110";
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constant opStoreR : opCodeType := "101111";
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subtype shRotCinType is std_ulogic_vector(2 downto 0);
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constant shRotLdC : shRotCinType := "00-";
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constant shRotLdM : shRotCinType := "01-";
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constant shRotLdL : shRotCinType := "10-";
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constant shRotLd0 : shRotCinType := "110";
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constant shRotLd1 : shRotCinType := "111";
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constant registerAddressBitNb : positive := $registerAddressBitNb;
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constant shRotPadLength : positive
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:= dataOut'length - opCodeType'length - registerAddressBitNb
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- 1 - shRotCinType'length;
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subtype shRotDirType is std_ulogic_vector(1+shRotPadLength-1 downto 0);
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constant shRotL : shRotDirType := (0 => '0', others => '-');
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constant shRotR : shRotDirType := (0 => '1', others => '-');
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subtype branchCodeType is std_ulogic_vector(4 downto 0);
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constant brRet : branchCodeType := "10101";
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constant brCall : branchCodeType := "11000";
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constant brJump : branchCodeType := "11010";
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constant brReti : branchCodeType := "11100";
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constant brEni : branchCodeType := "11110";
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subtype branchConditionType is std_ulogic_vector(2 downto 0);
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constant brDo : branchConditionType := "000";
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constant brZ : branchConditionType := "100";
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constant brNZ : branchConditionType := "101";
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constant brC : branchConditionType := "110";
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constant brNC : branchConditionType := "111";
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subtype memoryWordType is std_ulogic_vector(dataOut'range);
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type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType;
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signal memoryArray : memoryArrayType := (
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DONE
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open(asm2File, "<$asm2FileSpec") or die "Unable to open file, $!";
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while(my $line = <asm2File>) {
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chomp($line);
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# split code and comment
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my ($opcode, $comment) = split(/;/, $line, 2);
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if ( ($line =~ m/;/) and ($comment eq '') ) {
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$comment = ' ';
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}
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# addresses to VHDL
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my $address;
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if ($opcode) {
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($address, $opcode) = split(/:\s+/, $opcode, 2);
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$address = '16#' . $address . '# =>';
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$address = ' ' x ($vhdlAddressLength - length($address)) . $address;
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}
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# opcode to VHDL
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if ($opcode) {
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if ($comment eq '') {
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$comment = ' ' . $opcode;
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}
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else {
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$comment = ' ' . $opcode . ';' . $comment;
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}
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# replace NOP
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$opcode =~ s/\ANOP/LOAD s0, s0/;
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# split opcodes and operands
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$opcode =~ s/\s+/ /;
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$opcode =~ s/\s+\Z//;
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($opcode, my $operand1, my $operand2) = split(/\s/, $opcode);
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$operand1 =~ s/,//;
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$operand1 =~ s/S/s/;
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$operand2 =~ s/S/s/;
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if ( ($opcode =~ m/\ASL/) or ($opcode =~ m/\ASR/) ) {
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$operand2 = substr($opcode, 0, 3);
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$opcode = 'SHIFT';
|
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}
|
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if ( ($opcode =~ m/\ARL/) or ($opcode =~ m/\ARR/) ) {
|
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$operand2 = substr($opcode, 0, 2);
|
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$opcode = 'ROT';
|
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}
|
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if ( ($opcode eq 'JUMP') or ($opcode eq 'CALL') or ($opcode eq 'RETURN') ) {
|
||||
unless ($operand2) {
|
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unless ($opcode eq 'RETURN') {
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$operand2 = $operand1;
|
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}
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$operand1 = 'AW'; # AlWays
|
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}
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}
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#...........................................................................
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# opcodes to VHDL
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$opcode =~ s/LOAD/opLoadC/;
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$opcode =~ s/AND/opAndC/;
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$opcode =~ s/XOR/opXorC/;
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$opcode =~ s/ADDCY/opAddCyC/;
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$opcode =~ s/SUBCY/opSubCyC/;
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$opcode =~ s/ADD/opAddC/;
|
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$opcode =~ s/SUB/opSubC/;
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$opcode =~ s/SHIFT/opShRot/;
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$opcode =~ s/ROT/opShRot/;
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$opcode =~ s/COMPARE/opCompC/;
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$opcode =~ s/TEST/opTestC/;
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$opcode =~ s/FETCH/opFetchC/;
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$opcode =~ s/STORE/opStoreC/;
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||||
$opcode =~ s/OR/opOrC/;
|
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$opcode =~ s/INPUT/opInputC/;
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$opcode =~ s/OUTPUT/opOutputC/;
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$opcode =~ s/JUMP/brJump/;
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$opcode =~ s/CALL/brCall/;
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$opcode =~ s/RETURN/brRet/;
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if ($operand2 =~ m/s[0-9A-F]/) {
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$opcode =~ s/C\Z/R/;
|
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}
|
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$opcode = $opcode . ' ' x ($vhdlOpCodeLength - length($opcode)) . '& ';
|
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#...........................................................................
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# register as first operand
|
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if ($operand1 =~ m/s[0-9A-F]/) {
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$operand1 =~ s/\As//;
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$operand1 = '"' . toBinary($operand1, $registerAddressBitNb) . '"';
|
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}
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# test condition
|
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$operand1 =~ s/NC/brNC/;
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$operand1 =~ s/NZ/brNZ/;
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||||
$operand1 =~ s/\AC/brC/;
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||||
$operand1 =~ s/\AZ/brZ/;
|
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$operand1 =~ s/AW/brDo/;
|
||||
if ($opcode =~ m/brRet/) {
|
||||
$operand2 = 0;
|
||||
}
|
||||
if ($operand2 eq '') {
|
||||
$operand1 = $operand1 . ',';
|
||||
}
|
||||
$operand1 = $operand1 . ' ' x ($vhdlOperand1Length - length($operand1));
|
||||
unless ($operand2 eq '') {
|
||||
$operand1 = $operand1 . '& ';
|
||||
}
|
||||
#print "|$opcode| |$operand1| |$operand2|\n";
|
||||
#...........................................................................
|
||||
# register as second operand
|
||||
$operand2 =~ s/\A\((.*)\)\Z/$1/;
|
||||
if ($operand2 =~ m/s[0-9A-F]/) {
|
||||
$operand2 =~ s/\As//;
|
||||
$operand2 = toBinary($operand2, $registerAddressBitNb);
|
||||
if ($registerBitNb > $registerAddressBitNb) {
|
||||
$operand2 = $operand2 . '-' x ($registerBitNb - $registerAddressBitNb);
|
||||
if ($zeroDontCares) {
|
||||
$operand2 =~ s/\-/0/g;
|
||||
}
|
||||
}
|
||||
}
|
||||
# address as second operand
|
||||
elsif ($opcode =~ m/\Abr/) {
|
||||
my $fill = '';
|
||||
if ($binaryBranchInstructionLength < $binaryInstructionLength) {
|
||||
$fill = '-' x ($binaryInstructionLength - $binaryBranchInstructionLength);
|
||||
if ($zeroDontCares) {
|
||||
$fill =~ s/\-/0/g;
|
||||
}
|
||||
}
|
||||
if ( ($opcode =~ m/Ret/) ) {
|
||||
$operand2 = $fill . '-' x $addressBitNb;
|
||||
}
|
||||
else {
|
||||
$operand2 = $fill . toBinary(hex($operand2), $addressBitNb);
|
||||
}
|
||||
}
|
||||
# shift and rotate operators
|
||||
elsif ($opcode =~ m/opShRot/) {
|
||||
$operand2 =~ s/SL0/shRotL & shRotLd0/;
|
||||
$operand2 =~ s/SL1/shRotL & shRotLd1/;
|
||||
$operand2 =~ s/SLX/shRotL & shRotLdL/;
|
||||
$operand2 =~ s/SLA/shRotL & shRotLdC/;
|
||||
$operand2 =~ s/SR0/shRotR & shRotLd0/;
|
||||
$operand2 =~ s/SR1/shRotR & shRotLd1/;
|
||||
$operand2 =~ s/SRX/shRotR & shRotLdM/;
|
||||
$operand2 =~ s/SRA/shRotR & shRotLdC/;
|
||||
$operand2 =~ s/RL/shRotL & shRotLdH/;
|
||||
$operand2 =~ s/RR/shRotR & shRotLdL/;
|
||||
}
|
||||
# constant as second operand
|
||||
else {
|
||||
$operand2 = toBinary(hex($operand2), $registerBitNb);
|
||||
if ($registerAddressBitNb > $registerBitNb) {
|
||||
$operand2 = '-' x ($registerAddressBitNb - $registerBitNb) . $operand2;
|
||||
}
|
||||
}
|
||||
unless ($opcode =~ m/opShRot/) {
|
||||
$operand2 = '"' . $operand2 . '"';
|
||||
}
|
||||
# add separator at end
|
||||
if ($operand2) {
|
||||
$operand2 = $operand2 . ',';
|
||||
}
|
||||
#...........................................................................
|
||||
# concatenate opcode and operands
|
||||
$opcode = $opcode . $operand1 . $operand2;
|
||||
}
|
||||
else {
|
||||
$address = ' ' x $vhdlAddressLength;
|
||||
}
|
||||
# print VHDL code
|
||||
if ($keepComments == 0) {
|
||||
if ($opcode) {
|
||||
print vhdlFile "$address $opcode\n";
|
||||
}
|
||||
}
|
||||
else {
|
||||
$opcode = $opcode . ' ' x ($vhdlTotalLength - length($opcode));
|
||||
if ($comment) {
|
||||
$comment =~ s/\s+\Z//;
|
||||
print vhdlFile "$address $opcode--$comment\n";
|
||||
}
|
||||
else {
|
||||
print vhdlFile "$address $opcode\n";
|
||||
}
|
||||
}
|
||||
}
|
||||
close(asm2File);
|
||||
print vhdlFile <<DONE;
|
||||
others => (others => '0')
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
process (clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if en = '1' then
|
||||
dataOut <= memoryArray(to_integer(address));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END ARCHITECTURE mapped;
|
||||
DONE
|
||||
close(vhdlFile);
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
# Delete original file and copy VHDL file
|
||||
#
|
||||
if ($verbose > 0) {
|
||||
print "Copying $vhdlFileSpec to $outFileSpec\n";
|
||||
}
|
||||
|
||||
use File::Copy;
|
||||
unlink($outFileSpec);
|
||||
copy($vhdlFileSpec, $outFileSpec) or die "File cannot be copied.";
|
||||
#rename($vhdlFileSpec, $outFileSpec);
|
||||
|
||||
if ($verbose > 0) {
|
||||
print "$separator\n";
|
||||
}
|
||||
Reference in New Issue
Block a user