Initial commit

Libs/Memory/hdl/sdramControllerSampleDataIn_RTL.vhd

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+ARCHITECTURE RTL OF sdramControllerSampleDataIn IS
+BEGIN
+
+  sampleRamData: process(reset, clock)
+  begin
+    if reset = '1' then
+      ramDataIn <= (others => '0');
+    elsif falling_edge(clock) then
+      if sampleData = '1' then
+        ramDataIn <= memDataIn;
+      end if;
+    end if;
+  end process sampleRamData;
+
+
+END ARCHITECTURE RTL;
+