Klagarge/SEm-Labos
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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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Libs/Common_test/hdl/clockGenerator_sim.vhd Normal file
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ARCHITECTURE sim OF clockGenerator IS
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal clock_int: std_uLogic := '1';
BEGIN
reset <= '1', '0' after 2*clockPeriod;
clock_int <= not clock_int after clockPeriod/2;
clock <= transport clock_int after clockPeriod*9.0/10.0;
END ARCHITECTURE sim;