Initial commit

2024-02-23 13:01:05 +00:00
commit d212040c30
1914 changed files with 1290006 additions and 0 deletions
--- a/10-PipelinedOperators/PipelinedOperators_test/hdl/parallelAdder_tester_test.vhd
+++ b/10-PipelinedOperators/PipelinedOperators_test/hdl/parallelAdder_tester_test.vhd
@@ -0,0 +1,48 @@
+ARCHITECTURE test OF parallelAdder_tester IS
+
+  constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
+  signal sClock: std_uLogic := '1';
+  signal sReset: std_uLogic := '1';
+
+  constant aMax: signed(a'range) := (a'high => '0', others => '1');
+  constant aIncr: signed(a'range) := shift_right(aMax, 4)+1;
+  constant bIncr: signed(b'range) := shift_right(aMax, 4)+1;
+  signal a_int, b_int, sum_int: signed(a'range);
+
+BEGIN
+  ------------------------------------------------------------------------------
+                                                              -- clock and reset
+  sClock <= not sClock after clockPeriod/2;
+  sReset <= '1', '0' after 2*clockPeriod;
+
+  ------------------------------------------------------------------------------
+                                                                -- test sequence
+  process
+  begin
+    a_int <= (a_int'high => '1', others => '0');
+    b_int <= (b_int'high => '1', others => '0');
+    wait until sReset = '0';
+                                                                  -- data values
+    while a_int < aMax-aIncr loop
+      a_int <= a_int + aIncr;
+      b_int <= b_int + bIncr;
+      wait until rising_edge(sClock);
+      assert sum = a_int + b_int
+        report "sum is wrong !"
+        severity error;
+    end loop;
+                                                              -- stop simulation
+    assert false
+      report cr & cr &
+        "End of Simulation" &
+        cr
+      severity failure;
+    wait;
+  end process;
+
+  cIn <= '0';
+  a <= a_int;
+  b <= b_int;
+  sum_int <= a_int + b_int;
+
+END ARCHITECTURE test;