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623
10-PipelinedOperators/Board/concat/pipelinedOperators.vhd
Normal file
623
10-PipelinedOperators/Board/concat/pipelinedOperators.vhd
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-- VHDL Entity Board.pipelineCounter_ebs3.symbol
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 11:16:01 08.05.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY pipelineCounter_ebs3 IS
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GENERIC(
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counterBitNb : positive := 16
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);
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PORT(
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clock : IN std_ulogic;
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reset_n : IN std_ulogic;
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countOut : OUT unsigned (counterBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END pipelineCounter_ebs3 ;
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-- VHDL Entity PipelinedOperators.pipelineCounter.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 08:50:00 03/11/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY pipelineCounter IS
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GENERIC(
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bitNb : positive;
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stageNb : positive
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);
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PORT(
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countOut : OUT unsigned (bitNb-1 DOWNTO 0);
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clock : IN std_ulogic;
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reset : IN std_ulogic
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);
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-- Declarations
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END pipelineCounter ;
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-- VHDL Entity PipelinedOperators.pipelineAdder.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 08:50:15 03/11/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY pipelineAdder IS
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GENERIC(
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bitNb : positive;
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stageNb : positive
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);
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PORT(
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sum : OUT signed (bitNb-1 DOWNTO 0);
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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cIn : IN std_ulogic;
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cOut : OUT std_ulogic;
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a : IN signed (bitNb-1 DOWNTO 0);
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b : IN signed (bitNb-1 DOWNTO 0)
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);
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-- Declarations
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END pipelineAdder ;
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-- VHDL Entity PipelinedOperators.parallelAdder.symbol
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 11:43:49 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY parallelAdder IS
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GENERIC(
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bitNb : positive := 32
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);
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PORT(
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sum : OUT signed (bitNb-1 DOWNTO 0);
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cIn : IN std_ulogic;
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cOut : OUT std_ulogic;
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a : IN signed (bitNb-1 DOWNTO 0);
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b : IN signed (bitNb-1 DOWNTO 0)
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);
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-- Declarations
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END parallelAdder ;
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ARCHITECTURE masterVersion OF parallelAdder IS
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signal sum_int: unsigned(sum'high+1 downto 0);
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BEGIN
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sum_int <= resize(unsigned(a), sum_int'length) +
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resize(unsigned(b), sum_int'length) +
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resize('0' & cIn, sum_int'length);
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sum <= signed(sum_int(sum'range));
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cOut <= sum_int(sum_int'high);
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END ARCHITECTURE masterVersion;
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ARCHITECTURE masterVersion OF pipelineAdder IS
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constant stageBitNb : positive := sum'length/stageNb;
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subtype stageOperandType is signed(stageBitNb-1 downto 0);
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type stageOperandVectorType is array(stageNb-1 downto 0) of stageOperandType;
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type stageOperandMatrixType is array(stageNb-1 downto 0) of stageOperandVectorType;
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subtype carryType is std_ulogic_vector(stageNb downto 0);
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signal a_int, b_int, sum_int : stageOperandMatrixType;
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signal carryIn, carryOut : carryType;
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COMPONENT parallelAdder
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GENERIC (
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bitNb : positive := 32
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);
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PORT (
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sum : OUT signed (bitNb-1 DOWNTO 0);
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cIn : IN std_ulogic ;
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cOut : OUT std_ulogic ;
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a : IN signed (bitNb-1 DOWNTO 0);
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b : IN signed (bitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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carryIn(0) <= cIn;
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distributeInput: for wordIndex in stageOperandVectorType'range generate
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a_int(wordIndex)(0) <= a(wordIndex*stageBitNb+stageBitNb-1 downto wordIndex*stageBitNb);
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b_int(wordIndex)(0) <= b(wordIndex*stageBitNb+stageBitNb-1 downto wordIndex*stageBitNb);
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end generate distributeInput;
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inputRegistersX: for wordIndex in stageOperandVectorType'high downto 1 generate
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inputRegistersY: for pipeIndex in stageOperandMatrixType'high downto 1 generate
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upperTriangle: if wordIndex >= pipeIndex generate
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inputRegisters: process(reset, clock)
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begin
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if reset = '1' then
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a_int(wordIndex)(pipeIndex) <= (others => '0');
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b_int(wordIndex)(pipeIndex) <= (others => '0');
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elsif rising_edge(clock) then
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a_int(wordIndex)(pipeIndex) <= a_int(wordIndex)(pipeIndex-1);
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b_int(wordIndex)(pipeIndex) <= b_int(wordIndex)(pipeIndex-1);
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end if;
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end process inputRegisters;
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end generate upperTriangle;
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end generate inputRegistersY;
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end generate inputRegistersX;
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operation: for index in stageOperandVectorType'range generate
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partialAdder: parallelAdder
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GENERIC MAP (bitNb => stageBitNb)
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PORT MAP (
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a => a_int(index)(index),
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b => b_int(index)(index),
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sum => sum_int(index)(index),
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cIn => carryIn(index),
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cOut => carryOut(index)
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);
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carryRegisters: process(reset, clock)
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begin
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if reset = '1' then
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carryIn(index+1) <= '0';
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elsif rising_edge(clock) then
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carryIn(index+1) <= carryOut(index);
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end if;
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end process carryRegisters;
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end generate operation;
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outputRegistersX: for wordIndex in stageOperandVectorType'range generate
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outputRegistersY: for pipeIndex in stageOperandMatrixType'range generate
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lowerTriangle: if wordIndex < pipeIndex generate
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outputRegisters: process(reset, clock)
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begin
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if reset = '1' then
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sum_int(wordIndex)(pipeIndex) <= (others => '0');
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elsif rising_edge(clock) then
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sum_int(wordIndex)(pipeIndex) <= sum_int(wordIndex)(pipeIndex-1);
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end if;
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end process outputRegisters;
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end generate lowerTriangle;
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end generate outputRegistersY;
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end generate outputRegistersX;
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packOutput: for index in stageOperandVectorType'range generate
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sum(index*stageBitNb+stageBitNb-1 downto index*stageBitNb) <=
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sum_int(index)(stageOperandMatrixType'high);
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end generate packOutput;
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cOut <= carryOut(carryOut'high-1);
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END ARCHITECTURE masterVersion;
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ARCHITECTURE masterVersion OF pipelineCounter IS
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signal initCounter : unsigned(countOut'length/stageNb-1 downto 0);
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signal b : signed(countOut'range);
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signal sum : signed(countOut'range);
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COMPONENT pipelineAdder
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GENERIC (
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bitNb : positive := 32;
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stageNb : positive := 4
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);
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PORT (
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reset : IN std_ulogic;
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clock : IN std_ulogic;
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cIn : IN std_ulogic;
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a : IN signed (bitNb-1 DOWNTO 0);
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b : IN signed (bitNb-1 DOWNTO 0);
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sum : OUT signed (bitNb-1 DOWNTO 0);
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cOut : OUT std_ulogic
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);
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END COMPONENT;
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BEGIN
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adder: pipelineAdder
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GENERIC MAP (
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bitNb => countOut'length,
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stageNb => stageNb
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)
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PORT MAP (
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reset => reset,
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clock => clock,
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cIn => '0',
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a => sum,
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b => b,
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sum => sum,
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cOut => open
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);
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prepareBInput: process(reset, clock)
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begin
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if reset = '1' then
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initCounter <= (others => '0');
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elsif rising_edge(clock) then
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if initCounter < stageNb then
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initCounter <= initCounter + 1;
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end if;
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end if;
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end process prepareBInput;
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selectInitOrRun: process(initCounter, sum)
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begin
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if initCounter < stageNb-1 then
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b <= signed(resize(initCounter+stageNb-1, b'length));
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countOut <= resize(initCounter, countOut'length);
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else
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b <= to_signed(stageNb-1, b'length);
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countOut <= unsigned(sum);
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end if;
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end process selectInitOrRun;
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END ARCHITECTURE masterVersion;
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-- VHDL Entity Board.DFF.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:07:05 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY DFF IS
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PORT(
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CLK : IN std_uLogic;
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CLR : IN std_uLogic;
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D : IN std_uLogic;
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Q : OUT std_uLogic
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);
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-- Declarations
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END DFF ;
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ARCHITECTURE sim OF DFF IS
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BEGIN
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process(clk, clr)
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begin
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if clr = '1' then
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q <= '0';
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elsif rising_edge(clk) then
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q <= d;
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end if;
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end process;
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END ARCHITECTURE sim;
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-- VHDL Entity Board.inverterIn.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:07:14 02/19/19
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--
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||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY inverterIn IS
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PORT(
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in1 : IN std_uLogic;
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out1 : OUT std_uLogic
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);
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-- Declarations
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END inverterIn ;
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ARCHITECTURE sim OF inverterIn IS
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BEGIN
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out1 <= NOT in1;
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END ARCHITECTURE sim;
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-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
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-- Module Version: 5.7
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--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
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-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
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library IEEE;
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use IEEE.std_logic_1164.all;
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library ECP5U;
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use ECP5U.components.all;
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ENTITY pll IS
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PORT(
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clkIn100M : IN std_ulogic;
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en75M : IN std_ulogic;
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en50M : IN std_ulogic;
|
||||
en10M : IN std_ulogic;
|
||||
clk60MHz : OUT std_ulogic;
|
||||
clk75MHz : OUT std_ulogic;
|
||||
clk50MHz : OUT std_ulogic;
|
||||
clk10MHz : OUT std_ulogic;
|
||||
pllLocked : OUT std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END pll ;
|
||||
|
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architecture rtl of pll is
|
||||
|
||||
-- internal signal declarations
|
||||
signal REFCLK: std_logic;
|
||||
signal CLKOS3_t: std_logic;
|
||||
signal CLKOS2_t: std_logic;
|
||||
signal CLKOS_t: std_logic;
|
||||
signal CLKOP_t: std_logic;
|
||||
signal scuba_vhi: std_logic;
|
||||
signal scuba_vlo: std_logic;
|
||||
|
||||
attribute FREQUENCY_PIN_CLKOS3 : string;
|
||||
attribute FREQUENCY_PIN_CLKOS2 : string;
|
||||
attribute FREQUENCY_PIN_CLKOS : string;
|
||||
attribute FREQUENCY_PIN_CLKOP : string;
|
||||
attribute FREQUENCY_PIN_CLKI : string;
|
||||
attribute ICP_CURRENT : string;
|
||||
attribute LPF_RESISTOR : string;
|
||||
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
|
||||
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
|
||||
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
|
||||
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
|
||||
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
|
||||
attribute ICP_CURRENT of PLLInst_0 : label is "5";
|
||||
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
|
||||
attribute syn_keep : boolean;
|
||||
attribute NGD_DRC_MASK : integer;
|
||||
attribute NGD_DRC_MASK of rtl : architecture is 1;
|
||||
|
||||
begin
|
||||
-- component instantiation statements
|
||||
scuba_vhi_inst: VHI
|
||||
port map (Z=>scuba_vhi);
|
||||
|
||||
scuba_vlo_inst: VLO
|
||||
port map (Z=>scuba_vlo);
|
||||
|
||||
PLLInst_0: EHXPLLL
|
||||
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
|
||||
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
|
||||
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
|
||||
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
|
||||
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
|
||||
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
|
||||
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
|
||||
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
|
||||
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
|
||||
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
|
||||
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
|
||||
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
|
||||
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
|
||||
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
|
||||
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
|
||||
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
|
||||
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
|
||||
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
|
||||
|
||||
clk10MHz <= CLKOS3_t;
|
||||
clk50MHz <= CLKOS2_t;
|
||||
clk75MHz <= CLKOS_t;
|
||||
clk60MHz <= CLKOP_t;
|
||||
end rtl;
|
||||
|
||||
|
||||
|
||||
|
||||
--
|
||||
-- VHDL Architecture Board.pipelineCounter_ebs3.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 11:16:01 08.05.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
-- LIBRARY Board;
|
||||
-- LIBRARY Lattice;
|
||||
-- LIBRARY PipelinedOperators;
|
||||
|
||||
ARCHITECTURE struct OF pipelineCounter_ebs3 IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant pipelineStageNb: positive := 5;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL clk_sys : std_ulogic;
|
||||
SIGNAL logic0 : std_ulogic;
|
||||
SIGNAL logic1 : std_uLogic;
|
||||
SIGNAL reset : std_ulogic;
|
||||
SIGNAL resetSynch : std_ulogic;
|
||||
SIGNAL resetSynch_n : std_ulogic;
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT DFF
|
||||
PORT (
|
||||
CLK : IN std_uLogic ;
|
||||
CLR : IN std_uLogic ;
|
||||
D : IN std_uLogic ;
|
||||
Q : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT inverterIn
|
||||
PORT (
|
||||
in1 : IN std_uLogic ;
|
||||
out1 : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT pll
|
||||
PORT (
|
||||
clkIn100M : IN std_ulogic ;
|
||||
en75M : IN std_ulogic ;
|
||||
en50M : IN std_ulogic ;
|
||||
en10M : IN std_ulogic ;
|
||||
clk60MHz : OUT std_ulogic ;
|
||||
clk75MHz : OUT std_ulogic ;
|
||||
clk50MHz : OUT std_ulogic ;
|
||||
clk10MHz : OUT std_ulogic ;
|
||||
pllLocked : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT pipelineCounter
|
||||
GENERIC (
|
||||
bitNb : positive;
|
||||
stageNb : positive
|
||||
);
|
||||
PORT (
|
||||
countOut : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
-- FOR ALL : DFF USE ENTITY Board.DFF;
|
||||
-- FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||
-- FOR ALL : pipelineCounter USE ENTITY PipelinedOperators.pipelineCounter;
|
||||
-- FOR ALL : pll USE ENTITY Lattice.pll;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 5 eb5
|
||||
logic1 <= '1';
|
||||
|
||||
-- HDL Embedded Text Block 6 eb6
|
||||
logic0 <= '0';
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_dff : DFF
|
||||
PORT MAP (
|
||||
CLK => clock,
|
||||
CLR => reset,
|
||||
D => logic1,
|
||||
Q => resetSynch_n
|
||||
);
|
||||
I_inv1 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => reset_n,
|
||||
out1 => reset
|
||||
);
|
||||
I_inv2 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => resetSynch_n,
|
||||
out1 => resetSynch
|
||||
);
|
||||
I_pll : pll
|
||||
PORT MAP (
|
||||
clkIn100M => clock,
|
||||
en75M => logic0,
|
||||
en50M => logic0,
|
||||
en10M => logic0,
|
||||
clk60MHz => clk_sys,
|
||||
clk75MHz => OPEN,
|
||||
clk50MHz => OPEN,
|
||||
clk10MHz => OPEN,
|
||||
pllLocked => OPEN
|
||||
);
|
||||
I_cnt : pipelineCounter
|
||||
GENERIC MAP (
|
||||
bitNb => counterBitNb,
|
||||
stageNb => pipelineStageNb
|
||||
)
|
||||
PORT MAP (
|
||||
countOut => countOut,
|
||||
clock => clk_sys,
|
||||
reset => resetSynch
|
||||
);
|
||||
|
||||
END struct;
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user