Klagarge/SEm-Labos
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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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06-07-08-09-SystemOnChip/Board/hdl/inverterIn_sim.vhd Normal file
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ARCHITECTURE sim OF inverterIn IS
BEGIN
out1 <= NOT in1;
END ARCHITECTURE sim;