Klagarge/SEm-Labos
Archived
1
0
Fork 0
Code Activity

Initial commit

Browse Source
This commit is contained in:
github-classroom[bot]
2024-02-23 13:01:05 +00:00
committed by GitHub
commit d212040c30
1914 changed files with 1290006 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.ldf Normal file
View File

@@ -0,0 +1,22 @@
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="MyProjectTitle" device="LFE5U-25F-6BG256C" default_implementation="toplevel">
<Options/>
<Implementation title="toplevel" dir="toplevel" description="toplevel" synthesis="synplify" default_strategy="Strategy">
<Source name="../concat/did-synchro.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../concat/did-synchro.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="reveal_analyze.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/>
</Source>
<Source name="reveal_config.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
<Options/>
</Source>
<Source name="programmer.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy" file="strategy.sty"/>
</BaliProject>