Initial commit

2024-02-23 13:01:05 +00:00
commit d212040c30
1914 changed files with 1290006 additions and 0 deletions
--- a/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd
+++ b/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd
@@ -0,0 +1,13 @@
+ARCHITECTURE test OF lissajousGenerator_tester IS
+
+  constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
+  signal sClock: std_uLogic := '1';
+
+BEGIN
+  ------------------------------------------------------------------------------
+                                                              -- clock and reset
+  sClock <= not sClock after clockPeriod/2;
+  clock <= transport sClock after clockPeriod*9/10;
+  reset <= '1', '0' after 2*clockPeriod;
+
+END ARCHITECTURE test;