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add trigger + shift register + coeff

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This commit is contained in:
Rémi Heredero
2024-03-08 16:16:59 +01:00
parent 5c9f884e2f
commit cf05b0a7f9
8 changed files with 85 additions and 15 deletions
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11
02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd
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@@ -8,7 +8,7 @@ BEGIN
phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
sequenceTable: process(phase)
sequenceTable: process(phaseTableAddress)
begin
if phase(phase'high-1) = '1' then
phaseTableAddress2 <= 8 - phaseTableAddress;
@@ -30,9 +30,14 @@ BEGIN
when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
when others => quarterSine <= (others => '-');
end case;
if phaseTableAddress2 = 0 then
if phase(phase'high-1) = '1' then
quarterSine <= to_signed(16#7FFF#, quarterSine'length);
end if;
end if;
end process quarterTable;
invert: process(quarterSine)
invert: process(quarterSine, phase(phase'high))
begin
if phase(phase'high) = '1' then
sine <= NOT quarterSine;
@@ -40,7 +45,5 @@ BEGIN
sine <= quarterSine;
end if;
end process invert;
--sine <= quarterSine;
END ARCHITECTURE studentVersion;