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This commit is contained in:
Rémi Heredero
2024-03-15 15:03:34 +01:00
parent 3095603e39
commit 9ceb15c0ff
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zz-solutions/04-Lissajous/Board/hdl/inverter_sim.vhd Normal file
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ARCHITECTURE sim OF inverter IS
BEGIN
out1 <= NOT in1;
END ARCHITECTURE sim;