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Rémi Heredero
2024-03-15 15:03:34 +01:00
parent 3095603e39
commit 9ceb15c0ff
612 changed files with 272868 additions and 0 deletions
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zz-solutions/04-Lissajous/Board/diamond/lissajous.ldf Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="MyProjectTitle" device="LFE5U-25F-6BG256C" default_implementation="toplevel">
<Options/>
<Implementation title="toplevel" dir="toplevel" description="toplevel" synthesis="synplify" default_strategy="Strategy">
<Source name="../concat/did-synchro.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../concat/did-synchro.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="reveal_analyze.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/>
</Source>
<Source name="reveal_config.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
<Options/>
</Source>
<Source name="programmer.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy" file="strategy.sty"/>
</BaliProject>